Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0c6b93d2 authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Bjorn Helgaas
Browse files

arm64: dts: ls1046a: Add PCIe controller DT nodes 



LS1046a implements 3 PCIe 3.0 controllers.

Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarMinghuan Lian <minghuan.Lian@nxp.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent fc5c0b4d

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -661,6 +661,81 @@ 
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3400000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <4>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi1>, <&msi2>, <&msi3>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3500000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi2>, <&msi3>, <&msi1>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3600000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */

			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi3>, <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

		};



	};



	reserved-memory {