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Commit 0c466169 authored by Joakim Tjernlund's avatar Joakim Tjernlund Committed by Benjamin Herrenschmidt
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powerpc/8xx: Restore _PAGE_WRITETHRU 



8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.

Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?

Signed-off-by: default avatarJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 4a280a41

arch/powerpc/include/asm/pte-8xx.h

+3 −2
Original line number Diff line number Diff line
@@ -35,11 +35,12 @@ 
#define _PAGE_SPECIAL	0x0008	/* SW entry, forced to 0 by the TLB miss */

#define _PAGE_DIRTY	0x0100	/* C: page changed */



/* These 3 software bits must be masked out when the entry is loaded

 * into the TLB, 2 SW bits left.

/* These 4 software bits must be masked out when the entry is loaded

 * into the TLB, 1 SW bit left(0x0080).

 */

#define _PAGE_GUARDED	0x0010	/* software: guarded access */

#define _PAGE_ACCESSED	0x0020	/* software: page referenced */

#define _PAGE_WRITETHRU	0x0040	/* software: caching is write through */



/* Setting any bits in the nibble with the follow two controls will

 * require a TLB exception handler change.  It is assumed unused bits

arch/powerpc/kernel/head_8xx.S

+8 −0
Original line number Diff line number Diff line
@@ -422,6 +422,10 @@ DataStoreTLBMiss: 
	 * above.

	 */

	rlwimi	r11, r10, 0, 27, 27

	/* Insert the WriteThru flag into the TWC from the Linux PTE.

	 * It is bit 25 in the Linux PTE and bit 30 in the TWC

	 */

	rlwimi	r11, r10, 32-5, 30, 30

	DO_8xx_CPU6(0x3b80, r3)

	mtspr	SPRN_MD_TWC, r11
@@ -559,6 +563,10 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR 
	 * It is bit 27 of both the Linux PTE and the TWC

	 */

	rlwimi	r11, r10, 0, 27, 27

	/* Insert the WriteThru flag into the TWC from the Linux PTE.

	 * It is bit 25 in the Linux PTE and bit 30 in the TWC

	 */

	rlwimi	r11, r10, 32-5, 30, 30

	DO_8xx_CPU6(0x3b80, r3)

	mtspr	SPRN_MD_TWC, r11

	mfspr	r11, SPRN_MD_TWC	/* get the pte address again */