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Commit 0c325769 authored by Emmanuel Grumbach's avatar Emmanuel Grumbach Committed by John W. Linville
Browse files

iwlagn: move ISR related data to transport layer



Since the ISR is entirely in the transport layer, its data should be in the pcie
specific region.
Change sync_irq to first disable and then synchronize the IRQ.
iwl_isr and iwl_isr_ict now receive iwl_trans.

Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: default avatarWey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 57210f7c
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+2 −10
Original line number Diff line number Diff line
@@ -3627,7 +3627,6 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,

	IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
	priv->cfg = cfg;
	priv->inta_mask = CSR_INI_SET_MASK;

	/* is antenna coupling more than 35dB ? */
	priv->bt_ant_couple_ok =
@@ -3771,8 +3770,6 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,

void __devexit iwl_remove(struct iwl_priv * priv)
{
	unsigned long flags;

	wait_for_completion(&priv->firmware_loading_complete);

	IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
@@ -3801,13 +3798,8 @@ void __devexit iwl_remove(struct iwl_priv * priv)
	iwl_tt_exit(priv);

	/* make sure we flush any pending irq or
	 * tasklet for the driver
	 */
	spin_lock_irqsave(&priv->shrd->lock, flags);
	iwl_disable_interrupts(priv);
	spin_unlock_irqrestore(&priv->shrd->lock, flags);

	iwl_trans_sync_irq(trans(priv));
	 * tasklet for the driver */
	iwl_trans_disable_sync_irq(trans(priv));

	iwl_dealloc_ucode(priv);

+1 −12
Original line number Diff line number Diff line
@@ -1259,6 +1259,7 @@ struct iwl_priv {
	struct traffic_stats rx_stats;

	/* counts interrupts */
	/* TODO: move to the transport layer */
	struct isr_statistics isr_stats;

	struct iwl_power_mgr power_data;
@@ -1315,14 +1316,6 @@ struct iwl_priv {
	} accum_stats, delta_stats, max_delta_stats;
#endif

	/* INT ICT Table */
	__le32 *ict_tbl;
	void *ict_tbl_vir;
	dma_addr_t ict_tbl_dma;
	dma_addr_t aligned_ict_tbl_dma;
	int ict_index;
	u32 inta;
	bool use_ict;
	/*
	 * reporting the number of tids has AGG on. 0 means
	 * no AGGREGATION
@@ -1379,8 +1372,6 @@ struct iwl_priv {
	struct iwl_rxon_context *cur_rssi_ctx;
	bool bt_is_sco;

	u32 inta_mask;

	struct work_struct restart;
	struct work_struct scan_completed;
	struct work_struct abort_scan;
@@ -1398,8 +1389,6 @@ struct iwl_priv {
	struct work_struct bt_full_concurrency;
	struct work_struct bt_runtime_config;

	struct tasklet_struct irq_tasklet;

	struct delayed_work scan_check;

	/* TX Power */
+0 −21
Original line number Diff line number Diff line
@@ -132,33 +132,12 @@ static inline void iwl_wake_any_queue(struct iwl_priv *priv,

#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue

static inline void iwl_disable_interrupts(struct iwl_priv *priv)
{
	clear_bit(STATUS_INT_ENABLED, &priv->shrd->status);

	/* disable interrupts from uCode/NIC to host */
	iwl_write32(priv, CSR_INT_MASK, 0x00000000);

	/* acknowledge/clear/reset any interrupts still pending
	 * from uCode or flow handler (Rx/Tx DMA) */
	iwl_write32(priv, CSR_INT, 0xffffffff);
	iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
	IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
}

static inline void iwl_enable_rfkill_int(struct iwl_priv *priv)
{
	IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n");
	iwl_write32(priv, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
}

static inline void iwl_enable_interrupts(struct iwl_priv *priv)
{
	IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
	set_bit(STATUS_INT_ENABLED, &priv->shrd->status);
	iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
}

/**
 * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time
 * @priv -- pointer to iwl_priv data structure
+40 −5
Original line number Diff line number Diff line
@@ -78,6 +78,18 @@ struct iwl_trans_pcie {
	struct iwl_rx_queue rxq;
	struct work_struct rx_replenish;
	struct iwl_trans *trans;

	/* INT ICT Table */
	__le32 *ict_tbl;
	void *ict_tbl_vir;
	dma_addr_t ict_tbl_dma;
	dma_addr_t aligned_ict_tbl_dma;
	int ict_index;
	u32 inta;
	bool use_ict;
	struct tasklet_struct irq_tasklet;

	u32 inta_mask;
};

#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
@@ -87,7 +99,7 @@ struct iwl_trans_pcie {
* RX
******************************************************/
void iwl_bg_rx_replenish(struct work_struct *data);
void iwl_irq_tasklet(struct iwl_priv *priv);
void iwl_irq_tasklet(struct iwl_trans *trans);
void iwlagn_rx_replenish(struct iwl_trans *trans);
void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
			struct iwl_rx_queue *q);
@@ -96,12 +108,11 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
* ICT
******************************************************/
int iwl_reset_ict(struct iwl_priv *priv);
void iwl_disable_ict(struct iwl_priv *priv);
int iwl_alloc_isr_ict(struct iwl_priv *priv);
void iwl_free_isr_ict(struct iwl_priv *priv);
void iwl_disable_ict(struct iwl_trans *trans);
int iwl_alloc_isr_ict(struct iwl_trans *trans);
void iwl_free_isr_ict(struct iwl_trans *trans);
irqreturn_t iwl_isr_ict(int irq, void *data);


/*****************************************************
* TX / HCMD
******************************************************/
@@ -130,4 +141,28 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
						int frame_limit);

static inline void iwl_disable_interrupts(struct iwl_trans *trans)
{
	clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);

	/* disable interrupts from uCode/NIC to host */
	iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000);

	/* acknowledge/clear/reset any interrupts still pending
	 * from uCode or flow handler (Rx/Tx DMA) */
	iwl_write32(priv(trans), CSR_INT, 0xffffffff);
	iwl_write32(priv(trans), CSR_FH_INT_STATUS, 0xffffffff);
	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
}

static inline void iwl_enable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
	set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
	iwl_write32(priv(trans), CSR_INT_MASK, trans_pcie->inta_mask);
}

#endif /* __iwl_trans_int_pcie_h__ */
+179 −154

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