Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0bc89fcb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Update the QMP PHY init Sequence for Kona"

parents c8ce280a b4e4f15a
Loading
Loading
Loading
Loading
+8 −8
Original line number Diff line number Diff line
@@ -231,13 +231,13 @@
			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xFF 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0B 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB3 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
@@ -274,13 +274,13 @@
			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x7F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xFF 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x97 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0B 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB3 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
@@ -529,7 +529,7 @@
		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
		     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0
		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0
		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
@@ -543,7 +543,7 @@
		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0
		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0