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Commit 0b471506 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
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tg3: Recode PCI MRRS adjustment as a PCI quirk



This patch recodes the MRRS cap for 5719 A0 devices as a PCI quirk.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e19a82c1
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+0 −6
Original line number Diff line number Diff line
@@ -14242,12 +14242,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)

		tg3_flag_set(tp, PCI_EXPRESS);

		if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
			int readrq = pcie_get_readrq(tp->pdev);
			if (readrq > 2048)
				pcie_set_readrq(tp->pdev, 2048);
		}

		pci_read_config_word(tp->pdev,
				     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
				     &lnkctl);
+18 −0
Original line number Diff line number Diff line
@@ -2161,6 +2161,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_NX2_5709S,
			quirk_brcm_570x_limit_vpd);

static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
{
	u32 rev;

	pci_read_config_dword(dev, 0xf4, &rev);

	/* Only CAP the MRRS if the device is a 5719 A0 */
	if (rev == 0x05719000) {
		int readrq = pcie_get_readrq(dev);
		if (readrq > 2048)
			pcie_set_readrq(dev, 2048);
	}
}

DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
			 PCI_DEVICE_ID_TIGON3_5719,
			 quirk_brcm_5719_limit_mrrs);

/* Originally in EDAC sources for i82875P:
 * Intel tells BIOS developers to hide device 6 which
 * configures the overflow device access containing
+1 −0
Original line number Diff line number Diff line
@@ -2105,6 +2105,7 @@
#define PCI_DEVICE_ID_NX2_57711E	0x1650
#define PCI_DEVICE_ID_TIGON3_5705	0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
#define PCI_DEVICE_ID_TIGON3_5719	0x1657
#define PCI_DEVICE_ID_TIGON3_5721	0x1659
#define PCI_DEVICE_ID_TIGON3_5722	0x165a
#define PCI_DEVICE_ID_TIGON3_5723	0x165b