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Commit 0b382fb3 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next 

Freescale updates from Scott:

"Includes a fix for a powerpc/next mm regression on 64e, a fix for a
kernel hang on 64e when using a debugger inside a relocated kernel, a
qman fix, and misc qe improvements."
parents 6102c005 61baf155

Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt

+20 −1
Original line number Diff line number Diff line
@@ -13,8 +13,17 @@ Required properties: 
- #gpio-cells : Should be two. The first cell is the pin number and the

  second cell is used to specify optional parameters (currently unused).

- gpio-controller : Marks the port as GPIO controller.

Optional properties:

- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C

  on CPM1), this item tells which ports have an associated interrupt (ports are

  listed in the same order as in PCINT register)

- interrupts : This property provides the list of interrupt for each GPIO having

  one as described by the fsl,cpm1-gpio-irq-mask property. There should be as

  many interrupts as number of ones in the mask property. The first interrupt in

  the list corresponds to the most significant bit of the mask.

- interrupt-parent : Parent for the above interrupt property.



Example of three SOC GPIO banks defined as gpio-controller nodes:

Example of four SOC GPIO banks defined as gpio-controller nodes:



	CPM1_PIO_A: gpio-controller@950 {

		#gpio-cells = <2>;
@@ -30,6 +39,16 @@ Example of three SOC GPIO banks defined as gpio-controller nodes: 
		gpio-controller;

	};



	CPM1_PIO_C: gpio-controller@960 {

		#gpio-cells = <2>;

		compatible = "fsl,cpm1-pario-bank-c";

		reg = <0x960 0x10>;

		fsl,cpm1-gpio-irq-mask = <0x0fff>;

		interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;

		interrupt-parent = <&CPM_PIC>;

		gpio-controller;

	};



	CPM1_PIO_E: gpio-controller@ac8 {

		#gpio-cells = <2>;

		compatible = "fsl,cpm1-pario-bank-e";

arch/powerpc/include/asm/cpm1.h

+2 −0
Original line number Diff line number Diff line
@@ -560,6 +560,8 @@ typedef struct risc_timer_pram { 
#define CPM_PIN_SECONDARY 2

#define CPM_PIN_GPIO      4

#define CPM_PIN_OPENDRAIN 8

#define CPM_PIN_FALLEDGE  16

#define CPM_PIN_ANYEDGE   0



enum cpm_port {

	CPM_PORTA,

arch/powerpc/include/asm/processor.h

+5 −0
Original line number Diff line number Diff line
@@ -151,8 +151,13 @@ void release_thread(struct task_struct *); 


#ifdef __powerpc64__



#ifdef CONFIG_PPC_BOOK3S_64

/* Limit stack to 128TB */

#define STACK_TOP_USER64 TASK_SIZE_128TB

#else

#define STACK_TOP_USER64 TASK_SIZE_USER64

#endif



#define STACK_TOP_USER32 TASK_SIZE_USER32



#define STACK_TOP (is_32bit_task() ? \

arch/powerpc/kernel/exceptions-64e.S

+12 −0
Original line number Diff line number Diff line
@@ -735,8 +735,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 
	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h

	beq+	1f



#ifdef CONFIG_RELOCATABLE

	ld	r15,PACATOC(r13)

	ld	r14,interrupt_base_book3e@got(r15)

	ld	r15,__end_interrupts@got(r15)

#else

	LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)

	LOAD_REG_IMMEDIATE(r15,__end_interrupts)

#endif

	cmpld	cr0,r10,r14

	cmpld	cr1,r10,r15

	blt+	cr0,1f
@@ -799,8 +805,14 @@ kernel_dbg_exc: 
	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h

	beq+	1f



#ifdef CONFIG_RELOCATABLE

	ld	r15,PACATOC(r13)

	ld	r14,interrupt_base_book3e@got(r15)

	ld	r15,__end_interrupts@got(r15)

#else

	LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)

	LOAD_REG_IMMEDIATE(r15,__end_interrupts)

#endif

	cmpld	cr0,r10,r14

	cmpld	cr1,r10,r15

	blt+	cr0,1f

arch/powerpc/sysdev/cpm1.c

+25 −0
Original line number Diff line number Diff line
@@ -377,6 +377,10 @@ static void cpm1_set_pin16(int port, int pin, int flags) 
			setbits16(&iop->odr_sor, pin);

		else

			clrbits16(&iop->odr_sor, pin);

		if (flags & CPM_PIN_FALLEDGE)

			setbits16(&iop->intr, pin);

		else

			clrbits16(&iop->intr, pin);

	}

}
@@ -528,6 +532,9 @@ struct cpm1_gpio16_chip { 


	/* shadowed data register to clear/set bits safely */

	u16 cpdata;



	/* IRQ associated with Pins when relevant */

	int irq[16];

};



static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
@@ -578,6 +585,14 @@ static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) 
	spin_unlock_irqrestore(&cpm1_gc->lock, flags);

}



static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);



	return cpm1_gc->irq[gpio] ? : -ENXIO;

}



static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
@@ -618,6 +633,7 @@ int cpm1_gpiochip_add16(struct device_node *np) 
	struct cpm1_gpio16_chip *cpm1_gc;

	struct of_mm_gpio_chip *mm_gc;

	struct gpio_chip *gc;

	u16 mask;



	cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);

	if (!cpm1_gc)
@@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np) 


	spin_lock_init(&cpm1_gc->lock);



	if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {

		int i, j;



		for (i = 0, j = 0; i < 16; i++)

			if (mask & (1 << (15 - i)))

				cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);

	}



	mm_gc = &cpm1_gc->mm_gc;

	gc = &mm_gc->gc;
@@ -634,6 +658,7 @@ int cpm1_gpiochip_add16(struct device_node *np) 
	gc->direction_output = cpm1_gpio16_dir_out;

	gc->get = cpm1_gpio16_get;

	gc->set = cpm1_gpio16_set;

	gc->to_irq = cpm1_gpio16_to_irq;



	return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);

}