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Commit 0ae18865 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: remove g4x lowfreq_avail and has_pipe_cxsr 



They're unused and unsupported. Leave the reduced_clock pointers in
place still, should they prove useful later on.

v2: go from nuking DDI lowfreq_avail to nuking it entirely (Ville)

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171017140234.20677-1-jani.nikula@intel.com
parent d02ace87

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -785,7 +785,6 @@ struct intel_csr { 
	func(has_logical_ring_contexts); \

	func(has_logical_ring_preemption); \

	func(has_overlay); \

	func(has_pipe_cxsr); \

	func(has_pooled_eu); \

	func(has_psr); \

	func(has_rc6); \
@@ -3177,7 +3176,6 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)



#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)

#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)

#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)

#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)

drivers/gpu/drm/i915/i915_pci.c

+0 −2
Original line number Diff line number Diff line
@@ -193,7 +193,6 @@ static const struct intel_device_info intel_i965gm_info __initconst = { 
static const struct intel_device_info intel_g45_info __initconst = {

	GEN4_FEATURES,

	.platform = INTEL_G45,

	.has_pipe_cxsr = 1,

	.ring_mask = RENDER_RING | BSD_RING,

};
@@ -201,7 +200,6 @@ static const struct intel_device_info intel_gm45_info __initconst = { 
	GEN4_FEATURES,

	.platform = INTEL_GM45,

	.is_mobile = 1, .has_fbc = 1,

	.has_pipe_cxsr = 1,

	.supports_tv = 1,

	.ring_mask = RENDER_RING | BSD_RING,

};

drivers/gpu/drm/i915/intel_display.c

+0 −15
Original line number Diff line number Diff line
@@ -6438,11 +6438,9 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 


	crtc_state->dpll_hw_state.fp0 = fp;



	crtc->lowfreq_avail = false;

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

	    reduced_clock) {

		crtc_state->dpll_hw_state.fp1 = fp2;

		crtc->lowfreq_avail = true;

	} else {

		crtc_state->dpll_hw_state.fp1 = fp;

	}
@@ -7137,15 +7135,6 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 
		}

	}



	if (HAS_PIPE_CXSR(dev_priv)) {

		if (intel_crtc->lowfreq_avail) {

			DRM_DEBUG_KMS("enabling CxSR downclocking\n");

			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;

		} else {

			DRM_DEBUG_KMS("disabling CxSR downclocking\n");

		}

	}



	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

		if (INTEL_GEN(dev_priv) < 4 ||

		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
@@ -8281,8 +8270,6 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 
	memset(&crtc_state->dpll_hw_state, 0,

	       sizeof(crtc_state->dpll_hw_state));



	crtc->lowfreq_avail = false;



	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */

	if (!crtc_state->has_pch_encoder)

		return 0;
@@ -8941,8 +8928,6 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 
		}

	}



	crtc->lowfreq_avail = false;



	return 0;

}

drivers/gpu/drm/i915/intel_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -803,7 +803,6 @@ struct intel_crtc { 
	 * some outputs connected to this crtc.

	 */

	bool active;

	bool lowfreq_avail;

	u8 plane_ids_mask;

	unsigned long long enabled_power_domains;

	struct intel_overlay *overlay;