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Commit 0ace8217 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

ARM: dts: rockchip: add clock-cells for usb phy nodes 



Add the #clock-cells properties for the usbphy nodes as they
provide the pll-clocks now.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarMichael Turquette <mturquette@baylibre.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent df5ea015

arch/arm/boot/dts/rk3066a.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -202,6 +202,7 @@ 
			reg = <0x17c>;

			clocks = <&cru SCLK_OTGPHY0>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};



		usbphy1: usb-phy1 {
@@ -209,6 +210,7 @@ 
			reg = <0x188>;

			clocks = <&cru SCLK_OTGPHY1>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};

	};

arch/arm/boot/dts/rk3188.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ 
			reg = <0x10c>;

			clocks = <&cru SCLK_OTGPHY0>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};



		usbphy1: usb-phy1 {
@@ -178,6 +179,7 @@ 
			reg = <0x11c>;

			clocks = <&cru SCLK_OTGPHY1>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};

	};

arch/arm/boot/dts/rk3288.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -968,6 +968,7 @@ 
			reg = <0x320>;

			clocks = <&cru SCLK_OTGPHY0>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};



		usbphy1: usb-phy1 {
@@ -975,6 +976,7 @@ 
			reg = <0x334>;

			clocks = <&cru SCLK_OTGPHY1>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};



		usbphy2: usb-phy2 {
@@ -982,6 +984,7 @@ 
			reg = <0x348>;

			clocks = <&cru SCLK_OTGPHY2>;

			clock-names = "phyclk";

			#clock-cells = <0>;

		};

	};