Merge tag 'drm-misc-next-2018-04-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

		"adi,adv7513"

		"adi,adv7533"

- reg: I2C slave address

- reg: I2C slave addresses

  The ADV7511 internal registers are split into four pages exposed through

  different I2C addresses, creating four register maps. Each map has it own

  I2C address and acts as a standard slave device on the I2C bus. The main

  address is mandatory, others are optional and revert to defaults if not

  specified.

The ADV7511 supports a large number of input data formats that differ by their

color depth, color format, clock mode, bit justification and random

  rather than generate its own timings for HDMI output.

- clocks: from common clock binding: reference to the CEC clock.

- clock-names: from common clock binding: must be "cec".

- reg-names : Names of maps with programmable addresses.

	It can contain any map needing a non-default address.

	Possible maps names are : "main", "edid", "cec", "packet"

Required nodes:

	adv7511w: hdmi@39 {

		compatible = "adi,adv7511w";

		reg = <39>;

		/*

		 * The EDID page will be accessible on address 0x66 on the I2C

		 * bus. All other maps continue to use their default addresses.

		 */

		reg = <0x39>, <0x66>;

		reg-names = "main", "edid";

		interrupt-parent = <&gpio3>;

		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

		clocks = <&cec_clock>;

Cadence DSI bridge

==================

The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.

Required properties:

- compatible: should be set to "cdns,dsi".

- reg: physical base address and length of the controller's registers.

- interrupts: interrupt line connected to the DSI bridge.

- clocks: DSI bridge clocks.

- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".

- phys: phandle link to the MIPI D-PHY controller.

- phy-names: must contain "dphy".

- #address-cells: must be set to 1.

- #size-cells: must be set to 0.

Optional properties:

- resets: DSI reset lines.

- reset-names: can contain "dsi_p_rst".

Required subnodes:

- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.

  2 ports are available:

  * port 0: this port is only needed if some of your DSI devices are

	    controlled through  an external bus like I2C or SPI. Can have at

	    most 4 endpoints. The endpoint number is directly encoding the

	    DSI virtual channel used by this device.

  * port 1: represents the DPI input.

  Other ports will be added later to support the new kind of inputs.

- one subnode per DSI device connected on the DSI bus. Each DSI device should

  contain a reg property encoding its virtual channel.

Cadence DPHY

============

Cadence DPHY block.

Required properties:

- compatible: should be set to "cdns,dphy".

- reg: physical base address and length of the DPHY registers.

- clocks: DPHY reference clocks.

- clock-names: must contain "psm" and "pll_ref".

- #phy-cells: must be set to 0.

Example:

	dphy0: dphy@fd0e0000{

		compatible = "cdns,dphy";

		reg = <0x0 0xfd0e0000 0x0 0x1000>;

		clocks = <&psm_clk>, <&pll_ref_clk>;

		clock-names = "psm", "pll_ref";

		#phy-cells = <0>;

	};

	dsi0: dsi@fd0c0000 {

		compatible = "cdns,dsi";

		reg = <0x0 0xfd0c0000 0x0 0x1000>;

		clocks = <&pclk>, <&sysclk>;

		clock-names = "dsi_p_clk", "dsi_sys_clk";

		interrupts = <1>;

		phys = <&dphy0>;

		phy-names = "dphy";

		#address-cells = <1>;

		#size-cells = <0>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@1 {

				reg = <1>;

				dsi0_dpi_input: endpoint {

					remote-endpoint = <&xxx_dpi_output>;

				};

			};

		};

		panel: dsi-dev@0 {

			compatible = "<vendor,panel>";

			reg = <0>;

		};

	};

or

	dsi0: dsi@fd0c0000 {

		compatible = "cdns,dsi";

		reg = <0x0 0xfd0c0000 0x0 0x1000>;

		clocks = <&pclk>, <&sysclk>;

		clock-names = "dsi_p_clk", "dsi_sys_clk";

		interrupts = <1>;

		phys = <&dphy1>;

		phy-names = "dphy";

		#address-cells = <1>;

		#size-cells = <0>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				#address-cells = <1>;

				#size-cells = <0>;

				dsi0_output: endpoint@0 {

					reg = <0>;

					remote-endpoint = <&dsi_panel_input>;

				};

			};

			port@1 {

				reg = <1>;

				dsi0_dpi_input: endpoint {

					remote-endpoint = <&xxx_dpi_output>;

				};

			};

		};

	};

	i2c@xxx {

		panel: panel@59 {

			compatible = "<vendor,panel>";

			reg = <0x59>;

			port {

				dsi_panel_input: endpoint {

					remote-endpoint = <&dsi0_output>;

				};

			};

		};

	};

Thine Electronics THC63LVD1024 LVDS decoder

-------------------------------------------

The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams

to parallel data outputs. The chip supports single/dual input/output modes,

handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.

Single or dual operation mode, output data mapping and DDR output modes are

configured through input signals and the chip does not expose any control bus.

Required properties:

- compatible: Shall be "thine,thc63lvd1024"

- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,

  PPL and digital circuitry

Optional properties:

- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low

- oe-gpios: Output enable GPIO signal, pin name "OE". Active high

The THC63LVD1024 video port connections are modeled according

to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt

Required video port nodes:

- port@0: First LVDS input port

- port@2: First digital CMOS/TTL parallel output

Optional video port nodes:

- port@1: Second LVDS input port

- port@3: Second digital CMOS/TTL parallel output

Example:

--------

	thc63lvd1024: lvds-decoder {

		compatible = "thine,thc63lvd1024";

		vcc-supply = <&reg_lvds_vcc>;

		powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				lvds_dec_in_0: endpoint {

					remote-endpoint = <&lvds_out>;

				};

			};

			port@2{

				reg = <2>;

				lvds_dec_out_2: endpoint {

					remote-endpoint = <&adv7511_in>;

				};

			};

		};

	};

Allwinner A31 DSI Encoder

=========================

The DSI pipeline consists of two separate blocks: the DSI controller

itself, and its associated D-PHY.

DSI Encoder

-----------

The DSI Encoder generates the DSI signal from the TCON's.

Required properties:

  - compatible: value must be one of:

    * allwinner,sun6i-a31-mipi-dsi

  - reg: base address and size of memory-mapped region

  - interrupts: interrupt associated to this IP

  - clocks: phandles to the clocks feeding the DSI encoder

    * bus: the DSI interface clock

    * mod: the DSI module clock

  - clock-names: the clock names mentioned above

  - phys: phandle to the D-PHY

  - phy-names: must be "dphy"

  - resets: phandle to the reset controller driving the encoder

  - ports: A ports node with endpoint definitions as defined in

    Documentation/devicetree/bindings/media/video-interfaces.txt. The

    first port should be the input endpoint, usually coming from the

    associated TCON.

Any MIPI-DSI device attached to this should be described according to

the bindings defined in ../mipi-dsi-bus.txt

D-PHY

-----

Required properties:

  - compatible: value must be one of:

    * allwinner,sun6i-a31-mipi-dphy

  - reg: base address and size of memory-mapped region

  - clocks: phandles to the clocks feeding the DSI encoder

    * bus: the DSI interface clock

    * mod: the DSI module clock

  - clock-names: the clock names mentioned above

  - resets: phandle to the reset controller driving the encoder

Example:

dsi0: dsi@1ca0000 {

	compatible = "allwinner,sun6i-a31-mipi-dsi";

	reg = <0x01ca0000 0x1000>;

	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&ccu CLK_BUS_MIPI_DSI>,

		 <&ccu CLK_DSI_SCLK>;

	clock-names = "bus", "mod";

	resets = <&ccu RST_BUS_MIPI_DSI>;

	phys = <&dphy0>;

	phy-names = "dphy";

	#address-cells = <1>;

	#size-cells = <0>;

	panel@0 {

		compatible = "bananapi,lhr050h41", "ilitek,ili9881c";

		reg = <0>;

		power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */

		reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */

		backlight = <&pwm_bl>;

	};

	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

			dsi0_in_tcon0: endpoint {

				remote-endpoint = <&tcon0_out_dsi0>;

			};

		};

	};

};

dphy0: d-phy@1ca1000 {

	compatible = "allwinner,sun6i-a31-mipi-dphy";

	reg = <0x01ca1000 0x1000>;

	clocks = <&ccu CLK_BUS_MIPI_DSI>,

		 <&ccu CLK_DSI_DPHY>;

	clock-names = "bus", "mod";

	resets = <&ccu RST_BUS_MIPI_DSI>;

	#phy-cells = <0>;

};

   tve200

   vc4

   bridge/dw-hdmi

   xen-front

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