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Commit 0a6d80c7 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Ingo Molnar
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drivers/iommu/amd: Clean up iommu_pc_get_set_reg() 



Clean up coding style and fix a bug in the 64-bit register read logic
since it overwrites the upper 32-bit when reading the lower 32-bit.

Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Jörg Rödel <joro@8bytes.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: iommu@lists.linux-foundation.org
Link: http://lkml.kernel.org/r/1487926102-13073-5-git-send-email-Suravee.Suthikulpanit@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent dc6ca5e4

drivers/iommu/amd_iommu_init.c

+8 −5
Original line number Diff line number Diff line
@@ -2773,12 +2773,15 @@ static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu, 
		return -EINVAL;



	if (is_write) {

		writel((u32)*value, iommu->mmio_base + offset);

		writel((*value >> 32), iommu->mmio_base + offset + 4);

		u64 val = *value & GENMASK_ULL(47, 0);



		writel((u32)val, iommu->mmio_base + offset);

		writel((val >> 32), iommu->mmio_base + offset + 4);

	} else {

		*value = readl(iommu->mmio_base + offset + 4);

		*value <<= 32;

		*value = readl(iommu->mmio_base + offset);

		*value |= readl(iommu->mmio_base + offset);

		*value &= GENMASK_ULL(47, 0);

	}



	return 0;