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Commit 0a5f6e9d authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: handle broken disabled rb mask gracefully (6xx/7xx) (v2) 



This is a port of cedb655a
to older asics.  Fixes a possible divide by 0 if the harvest
register is invalid.

v2: drop some additional harvest munging.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 054e01d6

drivers/gpu/drm/radeon/r600.c

+8 −18
Original line number Diff line number Diff line
@@ -1812,7 +1812,6 @@ static void r600_gpu_init(struct radeon_device *rdev) 
{

	u32 tiling_config;

	u32 ramcfg;

	u32 cc_rb_backend_disable;

	u32 cc_gc_shader_pipe_config;

	u32 tmp;

	int i, j;
@@ -1939,29 +1938,20 @@ static void r600_gpu_init(struct radeon_device *rdev) 
	}

	tiling_config |= BANK_SWAPS(1);



	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;

	tmp = R6XX_MAX_BACKENDS -

		r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);

	if (tmp < rdev->config.r600.max_backends) {

		rdev->config.r600.max_backends = tmp;

	}



	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;

	tmp = R6XX_MAX_PIPES -

		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);

	if (tmp < rdev->config.r600.max_pipes) {

		rdev->config.r600.max_pipes = tmp;

	}

	tmp = R6XX_MAX_SIMDS -

		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);

	if (tmp < rdev->config.r600.max_simds) {

		rdev->config.r600.max_simds = tmp;

	}

	tmp = rdev->config.r600.max_simds -

		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);

	rdev->config.r600.active_simds = tmp;



	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;

	tmp = 0;

	for (i = 0; i < rdev->config.r600.max_backends; i++)

		tmp |= (1 << i);

	/* if all the backends are disabled, fix it up here */

	if ((disabled_rb_mask & tmp) == tmp) {

		for (i = 0; i < rdev->config.r600.max_backends; i++)

			disabled_rb_mask &= ~(1 << i);

	}

	tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;

	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,

					R6XX_MAX_BACKENDS, disabled_rb_mask);

drivers/gpu/drm/radeon/rv770.c

+8 −15
Original line number Diff line number Diff line
@@ -1177,7 +1177,6 @@ static void rv770_gpu_init(struct radeon_device *rdev) 
	u32 hdp_host_path_cntl;

	u32 sq_dyn_gpr_size_simd_ab_0;

	u32 gb_tiling_config = 0;

	u32 cc_rb_backend_disable = 0;

	u32 cc_gc_shader_pipe_config = 0;

	u32 mc_arb_ramcfg;

	u32 db_debug4, tmp;
@@ -1311,21 +1310,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) 
		WREG32(SPI_CONFIG_CNTL, 0);

	}



	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;

	tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);

	if (tmp < rdev->config.rv770.max_backends) {

		rdev->config.rv770.max_backends = tmp;

	}



	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;

	tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);

	if (tmp < rdev->config.rv770.max_pipes) {

		rdev->config.rv770.max_pipes = tmp;

	}

	tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);

	if (tmp < rdev->config.rv770.max_simds) {

		rdev->config.rv770.max_simds = tmp;

	}

	tmp = rdev->config.rv770.max_simds -

		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);

	rdev->config.rv770.active_simds = tmp;
@@ -1348,6 +1333,14 @@ static void rv770_gpu_init(struct radeon_device *rdev) 
	rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;



	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;

	tmp = 0;

	for (i = 0; i < rdev->config.rv770.max_backends; i++)

		tmp |= (1 << i);

	/* if all the backends are disabled, fix it up here */

	if ((disabled_rb_mask & tmp) == tmp) {

		for (i = 0; i < rdev->config.rv770.max_backends; i++)

			disabled_rb_mask &= ~(1 << i);

	}

	tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;

	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,

					R7XX_MAX_BACKENDS, disabled_rb_mask);