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Commit 0a30284b authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Geert Uytterhoeven
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clk: renesas: r8a7795: Fix HDMI parent clock 



Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e6e35586

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 
	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),



	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),

	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),

	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),