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Commit 0a073b84 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: turbo & RC6 support for VLV v7 



Uses slightly different interfaces than other platforms.

v2: track actual set freq, not requested (Rohit)
    fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
    re-add RC6 wake limit write (Ben)
    fixup thresholds to match other platforms (Ben)
    clean up mem freq calculation (Ben)
    clean up debug prints (Ben)
v4: move defines from punit patch (Ville)
v5: remove writes to nonexistent regs (Jesse)
    put RP and RC regs together (Jesse)
    fix RC6 enable (Jesse)
v6: use correct fuse reads from NC (Jesse)
    split out min/max funcs for use in sysfs (Jesse)
    add debugfs & sysfs freq controls (Jesse)
v7: update with Ben's hw_max changes (Jesse)

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v6)
[danvet: Follow checkpatch sugggestion to use min_t to avoid casting
fun.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 855ba3be

drivers/gpu/drm/i915/i915_debugfs.c

+49 −9
Original line number Diff line number Diff line
@@ -941,7 +941,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
			   MEMSTAT_VID_SHIFT);

		seq_printf(m, "Current P-state: %d\n",

			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);

	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {

	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {

		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);

		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1009,6 +1009,25 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 


		seq_printf(m, "Max overclocked frequency: %dMHz\n",

			   dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);

	} else if (IS_VALLEYVIEW(dev)) {

		u32 freq_sts, val;



		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,

				      &freq_sts);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);



		valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);

		seq_printf(m, "max GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv->mem_freq, val));



		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);

		seq_printf(m, "min GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv->mem_freq, val));



		seq_printf(m, "current GPU freq: %d MHz\n",

			   vlv_gpu_freq(dev_priv->mem_freq,

					(freq_sts >> 8) & 0xff));

	} else {

		seq_printf(m, "no P-state info available\n");

	}
@@ -1812,6 +1831,10 @@ i915_max_freq_get(void *data, u64 *val) 
	if (ret)

		return ret;



	if (IS_VALLEYVIEW(dev))

		*val = vlv_gpu_freq(dev_priv->mem_freq,

				    dev_priv->rps.max_delay);

	else

		*val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -1837,9 +1860,16 @@ i915_max_freq_set(void *data, u64 val) 
	/*

	 * Turbo will still be enabled, but won't go above the set value.

	 */

	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv->mem_freq, val);

		dev_priv->rps.max_delay = val;

		gen6_set_rps(dev, val);

	} else {

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		dev_priv->rps.max_delay = val;

		gen6_set_rps(dev, val);

	}



	mutex_unlock(&dev_priv->rps.hw_lock);



	return 0;
@@ -1863,6 +1893,10 @@ i915_min_freq_get(void *data, u64 *val) 
	if (ret)

		return ret;



	if (IS_VALLEYVIEW(dev))

		*val = vlv_gpu_freq(dev_priv->mem_freq,

				    dev_priv->rps.min_delay);

	else

		*val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -1888,9 +1922,15 @@ i915_min_freq_set(void *data, u64 val) 
	/*

	 * Turbo will still be enabled, but won't go below the set value.

	 */

	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv->mem_freq, val);

		dev_priv->rps.min_delay = val;

		valleyview_set_rps(dev, val);

	} else {

		do_div(val, GT_FREQUENCY_MULTIPLIER);

		dev_priv->rps.min_delay = val;

		gen6_set_rps(dev, val);

	}

	mutex_unlock(&dev_priv->rps.hw_lock);



	return 0;

drivers/gpu/drm/i915/i915_drv.h

+5 −0
Original line number Diff line number Diff line
@@ -1856,6 +1856,9 @@ extern void intel_disable_fbc(struct drm_device *dev); 
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);

extern void intel_init_pch_refclk(struct drm_device *dev);

extern void gen6_set_rps(struct drm_device *dev, u8 val);

extern void valleyview_set_rps(struct drm_device *dev, u8 val);

extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);

extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);

extern void intel_detect_pch(struct drm_device *dev);

extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);

extern int intel_enable_rc6(const struct drm_device *dev);
@@ -1887,6 +1890,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);

int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);

int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);

int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);



int vlv_gpu_freq(int ddr_freq, int val);

int vlv_freq_opcode(int ddr_freq, int val);

drivers/gpu/drm/i915/i915_irq.c

+4 −1
Original line number Diff line number Diff line
@@ -482,6 +482,9 @@ static void gen6_pm_rps_work(struct work_struct *work) 
	 */

	if (!(new_delay > dev_priv->rps.max_delay ||

	      new_delay < dev_priv->rps.min_delay)) {

		if (IS_VALLEYVIEW(dev_priv->dev))

			valleyview_set_rps(dev_priv->dev, new_delay);

		else

			gen6_set_rps(dev_priv->dev, new_delay);

	}

drivers/gpu/drm/i915/i915_reg.h

+21 −0
Original line number Diff line number Diff line
@@ -4315,6 +4315,7 @@ 
#define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)

#define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)

#define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)

#define   GEN7_RC_CTL_TO_MODE			(1<<28)

#define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)

#define   GEN6_RC_CTL_HW_ENABLE			(1<<31)

#define GEN6_RP_DOWN_TIMEOUT			0xA010
@@ -4406,12 +4407,32 @@ 
#define   IOSF_BAR_SHIFT			1

#define   IOSF_SB_BUSY				(1<<0)

#define   IOSF_PORT_PUNIT			0x4

#define   IOSF_PORT_NC				0x11

#define VLV_IOSF_DATA				0x182104

#define VLV_IOSF_ADDR				0x182108



#define PUNIT_OPCODE_REG_READ			6

#define PUNIT_OPCODE_REG_WRITE			7



#define PUNIT_REG_GPU_LFM			0xd3

#define PUNIT_REG_GPU_FREQ_REQ			0xd4

#define PUNIT_REG_GPU_FREQ_STS			0xd8

#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc



#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */



#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c

#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3

#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11

#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800

#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34

#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007

#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30

#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27

#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000



#define GEN6_GT_CORE_STATUS		0x138060

#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)

#define   GEN6_RCn_MASK			7

drivers/gpu/drm/i915/i915_sysfs.c

+52 −19
Original line number Diff line number Diff line
@@ -212,6 +212,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 
	int ret;



	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev_priv->dev))

		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay);

	else

		ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -226,6 +229,9 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute 
	int ret;



	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev_priv->dev))

		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);

	else

		ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -246,16 +252,25 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, 
	if (ret)

		return ret;



	val /= GT_FREQUENCY_MULTIPLIER;



	mutex_lock(&dev_priv->rps.hw_lock);



	if (IS_VALLEYVIEW(dev_priv->dev)) {

		val = vlv_freq_opcode(dev_priv->mem_freq, val);



		hw_max = valleyview_rps_max_freq(dev_priv);

		hw_min = valleyview_rps_min_freq(dev_priv);

		non_oc_max = hw_max;

	} else {

		val /= GT_FREQUENCY_MULTIPLIER;



		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

		hw_max = dev_priv->rps.hw_max;

		non_oc_max = (rp_state_cap & 0xff);

		hw_min = ((rp_state_cap & 0xff0000) >> 16);

	}



	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {

	if (val < hw_min || val > hw_max ||

	    val < dev_priv->rps.min_delay) {

		mutex_unlock(&dev_priv->rps.hw_lock);

		return -EINVAL;

	}
@@ -264,8 +279,12 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, 
		DRM_DEBUG("User requested overclocking to %d\n",

			  val * GT_FREQUENCY_MULTIPLIER);



	if (dev_priv->rps.cur_delay > val)

	if (dev_priv->rps.cur_delay > val) {

		if (IS_VALLEYVIEW(dev_priv->dev))

			valleyview_set_rps(dev_priv->dev, val);

		else

			gen6_set_rps(dev_priv->dev, val);

	}



	dev_priv->rps.max_delay = val;
@@ -282,6 +301,9 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute 
	int ret;



	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev_priv->dev))

		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);

	else

		ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -302,21 +324,32 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, 
	if (ret)

		return ret;



	val /= GT_FREQUENCY_MULTIPLIER;



	mutex_lock(&dev_priv->rps.hw_lock);



	if (IS_VALLEYVIEW(dev)) {

		val = vlv_freq_opcode(dev_priv->mem_freq, val);



		hw_max = valleyview_rps_max_freq(dev_priv);

		hw_min = valleyview_rps_min_freq(dev_priv);

	} else {

		val /= GT_FREQUENCY_MULTIPLIER;



		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

		hw_max = dev_priv->rps.hw_max;

		hw_min = ((rp_state_cap & 0xff0000) >> 16);

	}



	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {

		mutex_unlock(&dev_priv->rps.hw_lock);

		return -EINVAL;

	}



	if (dev_priv->rps.cur_delay < val)

	if (dev_priv->rps.cur_delay < val) {

		if (IS_VALLEYVIEW(dev))

			valleyview_set_rps(dev, val);

		else

			gen6_set_rps(dev_priv->dev, val);

	}



	dev_priv->rps.min_delay = val;