Commit 09c87db8 authored Apr 03, 2014 by Imre Deak Committed by Daniel Vetter Apr 04, 2014

drm/i915: vlv: fix RPS interrupt mask setting



This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent f6d51948

drivers/gpu/drm/i915/intel_pm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3159,7 +3159,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
		if (val != dev_priv->rps.cur_freq)
		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);

		I915_WRITE(GEN6_PMINTRMSK, val);
		I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));

		dev_priv->rps.cur_freq = val;
		trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));