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Commit 0989b090 authored by Brian Norris's avatar Brian Norris
Browse files

Merge tag 'nand/for-4.10' of github.com:linux-nand/linux 

From Boris Brezillon:

"""
This pull request contains the following notable changes:
- new tango NAND controller driver
- new ox820 NAND controller driver
- addition of a new full-ID entry in the nand_ids table
- rework of the s3c240 driver to support DT
- extension of the nand_sdr_timings to expose tCCS, tPROG and tR
- addition of a new flag to ask the core to wait for tCCS when sending
  a RNDIN/RNDOUT command
- addition of a new flag to ask the core to let the controller driver
  send the READ/PROGPAGE command

This pull request also contains minor fixes/cleanup/cosmetic changes:
- properly support 512 ECC step size in the sunxi driver
- improve the error messages in the pxa probe path
- fix module autoload in the omap2 driver
- cleanup of several nand drivers to return nand_scan{_tail}() error
  code instead of returning -EIO
- various cleanups in the denali driver
- cleanups in the ooblayout handling (MTD core)
- fix an error check in nandsim
"""
parents b2c4ba5c 8fcfba07

Documentation/devicetree/bindings/mtd/oxnas-nand.txt

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* Oxford Semiconductor OXNAS NAND Controller



Please refer to nand.txt for generic information regarding MTD NAND bindings.



Required properties:

 - compatible: "oxsemi,ox820-nand"

 - reg: Base address and length for NAND mapped memory.



Optional Properties:

 - clocks: phandle to the NAND gate clock if needed.

 - resets: phandle to the NAND reset control if needed.



Example:



nandc: nand-controller@41000000 {

	compatible = "oxsemi,ox820-nand";

	reg = <0x41000000 0x100000>;

	clocks = <&stdclk CLK_820_NAND>;

	resets = <&reset RESET_NAND>;

	#address-cells = <1>;

	#size-cells = <0>;



	nand@0 {

		reg = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		nand-ecc-mode = "soft";

		nand-ecc-algo = "hamming";



		partition@0 {

			label = "boot";

			reg = <0x00000000 0x00e00000>;

			read-only;

		};



		partition@e00000 {

			label = "ubi";

			reg = <0x00e00000 0x07200000>;

		};

	};

};

Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt

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* Samsung S3C2410 and compatible NAND flash controller



Required properties:

- compatible : The possible values are:

	"samsung,s3c2410-nand"

	"samsung,s3c2412-nand"

	"samsung,s3c2440-nand"

- reg : register's location and length.

- #address-cells, #size-cells : see nand.txt

- clocks : phandle to the nand controller clock

- clock-names : must contain "nand"



Optional child nodes:

Child nodes representing the available nand chips.



Optional child properties:

- nand-ecc-mode : see nand.txt

- nand-on-flash-bbt : see nand.txt



Each child device node may optionally contain a 'partitions' sub-node,

which further contains sub-nodes describing the flash partition mapping.

See partition.txt for more detail.



Example:



nand-controller@4e000000 {

	compatible = "samsung,s3c2440-nand";

	reg = <0x4e000000 0x40>;



	#address-cells = <1>;

        #size-cells = <0>;



	clocks = <&clocks HCLK_NAND>;

	clock-names = "nand";



	nand {

		nand-ecc-mode = "soft";

		nand-on-flash-bbt;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			partition@0 {

				label = "u-boot";

				reg = <0 0x040000>;

			};



			partition@40000 {

				label = "kernel";

				reg = <0x040000 0x500000>;

			};

		};

	};

};

Documentation/devicetree/bindings/mtd/tango-nand.txt

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Sigma Designs Tango4 NAND Flash Controller (NFC)



Required properties:



- compatible: "sigma,smp8758-nand"

- reg: address/size of nfc_reg, nfc_mem, and pbus_reg

- dmas: reference to the DMA channel used by the controller

- dma-names: "nfc_sbox"

- clocks: reference to the system clock

- #address-cells: <1>

- #size-cells: <0>



Children nodes represent the available NAND chips.

See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.



Example:



	nandc: nand-controller@2c000 {

		compatible = "sigma,smp8758-nand";

		reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;

		dmas = <&dma0 3>;

		dma-names = "nfc_sbox";

		clocks = <&clkgen SYS_CLK>;

		#address-cells = <1>;

		#size-cells = <0>;



		nand@0 {

			reg = <0>; /* CS0 */

			nand-ecc-strength = <14>;

			nand-ecc-step-size = <1024>;

		};



		nand@1 {

			reg = <1>; /* CS1 */

			nand-ecc-strength = <14>;

			nand-ecc-step-size = <1024>;

		};

	};

arch/arm/mach-s3c24xx/common-smdk.c

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@@ -171,6 +171,7 @@ static struct s3c2410_platform_nand smdk_nand_info = { 
	.twrph1		= 20,

	.nr_sets	= ARRAY_SIZE(smdk_nand_sets),

	.sets		= smdk_nand_sets,

	.ecc_mode       = NAND_ECC_SOFT,

};



/* devices we initialise */

arch/arm/mach-s3c24xx/mach-anubis.c

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@@ -223,6 +223,7 @@ static struct s3c2410_platform_nand __initdata anubis_nand_info = { 
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),

	.sets		= anubis_nand_sets,

	.select_chip	= anubis_nand_select,

	.ecc_mode       = NAND_ECC_SOFT,

};



/* IDE channels */