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Unverified Commit 09773c53 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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drm/sun4i: Enable DW HDMI PHY clock 



Current DW HDMI PHY code never prepares and enables PHY clock after it is
created. It's just used as it is. This may work in some cases, but it's
clearly wrong. Fix it by adding proper calls to enable/disable PHY
clock.

Fixes: 4f86e817 ("drm/sun4i: Add support for H3 HDMI PHY variant")

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-17-jernej.skrabec@siol.net
parent 03c35dbf

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

+6 −1
Original line number Diff line number Diff line
@@ -477,13 +477,15 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
			dev_err(dev, "Couldn't create the PHY clock\n");

			goto err_put_clk_pll0;

		}



		clk_prepare_enable(phy->clk_phy);

	}



	phy->rst_phy = of_reset_control_get_shared(node, "phy");

	if (IS_ERR(phy->rst_phy)) {

		dev_err(dev, "Could not get phy reset control\n");

		ret = PTR_ERR(phy->rst_phy);

		goto err_put_clk_pll0;

		goto err_disable_clk_phy;

	}



	ret = reset_control_deassert(phy->rst_phy);
@@ -514,6 +516,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
	reset_control_assert(phy->rst_phy);

err_put_rst_phy:

	reset_control_put(phy->rst_phy);

err_disable_clk_phy:

	clk_disable_unprepare(phy->clk_phy);

err_put_clk_pll0:

	if (phy->variant->has_phy_clk)

		clk_put(phy->clk_pll0);
@@ -531,6 +535,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) 


	clk_disable_unprepare(phy->clk_mod);

	clk_disable_unprepare(phy->clk_bus);

	clk_disable_unprepare(phy->clk_phy);



	reset_control_assert(phy->rst_phy);