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Commit 0908180b authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Classify the engines in class + instance 



In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

v3: Don't use enums for bspec-defined stuff (Michal)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491834873-9345-2-git-send-email-oscar.mateo@intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent f42bb651

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -85,6 +85,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define VECS_HW		3

#define VCS2_HW		4



/* Engine class */



#define RENDER_CLASS		0

#define VIDEO_DECODE_CLASS	1

#define VIDEO_ENHANCEMENT_CLASS	2

#define COPY_ENGINE_CLASS	3

#define OTHER_CLASS		4



/* PCI config space */



#define MCHBAR_I915 0x44

drivers/gpu/drm/i915/intel_engine_cs.c

+14 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ static const struct engine_info { 
	const char *name;

	unsigned int exec_id;

	unsigned int hw_id;

	u8 class;

	u8 instance;

	u32 mmio_base;

	unsigned irq_shift;

	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@ static const struct engine_info { 
		.name = "rcs",

		.hw_id = RCS_HW,

		.exec_id = I915_EXEC_RENDER,

		.class = RENDER_CLASS,

		.instance = 0,

		.mmio_base = RENDER_RING_BASE,

		.irq_shift = GEN8_RCS_IRQ_SHIFT,

		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@ static const struct engine_info { 
		.name = "bcs",

		.hw_id = BCS_HW,

		.exec_id = I915_EXEC_BLT,

		.class = COPY_ENGINE_CLASS,

		.instance = 0,

		.mmio_base = BLT_RING_BASE,

		.irq_shift = GEN8_BCS_IRQ_SHIFT,

		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@ static const struct engine_info { 
		.name = "vcs",

		.hw_id = VCS_HW,

		.exec_id = I915_EXEC_BSD,

		.class = VIDEO_DECODE_CLASS,

		.instance = 0,

		.mmio_base = GEN6_BSD_RING_BASE,

		.irq_shift = GEN8_VCS1_IRQ_SHIFT,

		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@ static const struct engine_info { 
		.name = "vcs2",

		.hw_id = VCS2_HW,

		.exec_id = I915_EXEC_BSD,

		.class = VIDEO_DECODE_CLASS,

		.instance = 1,

		.mmio_base = GEN8_BSD2_RING_BASE,

		.irq_shift = GEN8_VCS2_IRQ_SHIFT,

		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@ static const struct engine_info { 
		.name = "vecs",

		.hw_id = VECS_HW,

		.exec_id = I915_EXEC_VEBOX,

		.class = VIDEO_ENHANCEMENT_CLASS,

		.instance = 0,

		.mmio_base = VEBOX_RING_BASE,

		.irq_shift = GEN8_VECS_IRQ_SHIFT,

		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, 
	engine->hw_id = engine->guc_id = info->hw_id;

	engine->mmio_base = info->mmio_base;

	engine->irq_shift = info->irq_shift;

	engine->class = info->class;

	engine->instance = info->instance;



	/* Nothing to do here, execute in order of dependencies */

	engine->schedule = NULL;

drivers/gpu/drm/i915/intel_ringbuffer.h

+4 −0
Original line number Diff line number Diff line
@@ -193,6 +193,10 @@ struct intel_engine_cs { 
	enum intel_engine_id id;

	unsigned int exec_id;

	unsigned int hw_id;



	u8 class;

	u8 instance;



	unsigned int guc_id;

	u32		mmio_base;

	unsigned int irq_shift;