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Commit 08dcc57f authored by Ben Goz's avatar Ben Goz Committed by Oded Gabbay
Browse files

drm/radeon: Initialize compute vmid 



This patch moves to radeon the initialization of compute vmid.

That initializations was done in kfd-->kgd interface, but doing it in radeon
as part of radeon's H/W initialization routines is more appropriate.

In addition, this simplifies the kfd-->kgd interface.

The patch removes the function from the interface file and from the interface
declaration file.

The function initializes memory apertures to fixed base/limit address and non
cached memory types.

Signed-off-by: default avatarBen Goz <ben.goz@amd.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc839753

drivers/gpu/drm/amd/include/kgd_kfd_interface.h

+0 −4
Original line number Diff line number Diff line
@@ -129,9 +129,6 @@ struct kgd2kfd_calls { 
 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp

 * scheduling mode. Only used for no cp scheduling mode.

 *

 * @init_memory: Initializes memory apertures to fixed base/limit address

 * and non cached memory types.

 *

 * @init_pipeline: Initialized the compute pipelines.

 *

 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
@@ -175,7 +172,6 @@ struct kfd2kgd_calls { 
	int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,

					unsigned int vmid);



	int (*init_memory)(struct kgd_dev *kgd);

	int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id,

				uint32_t hpd_size, uint64_t hpd_gpu_addr);

drivers/gpu/drm/radeon/cik.c

+24 −0
Original line number Diff line number Diff line
@@ -5707,6 +5707,28 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev) 
	WREG32(VM_INVALIDATE_REQUEST, 0x1);

}



static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)

{

	int i;

	uint32_t sh_mem_bases, sh_mem_config;



	sh_mem_bases = 0x6000 | 0x6000 << 16;

	sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);

	sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);



	mutex_lock(&rdev->srbm_mutex);

	for (i = 8; i < 16; i++) {

		cik_srbm_select(rdev, 0, 0, 0, i);

		/* CP and shaders */

		WREG32(SH_MEM_CONFIG, sh_mem_config);

		WREG32(SH_MEM_APE1_BASE, 1);

		WREG32(SH_MEM_APE1_LIMIT, 0);

		WREG32(SH_MEM_BASES, sh_mem_bases);

	}

	cik_srbm_select(rdev, 0, 0, 0, 0);

	mutex_unlock(&rdev->srbm_mutex);

}



/**

 * cik_pcie_gart_enable - gart enable

 *
@@ -5820,6 +5842,8 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	cik_srbm_select(rdev, 0, 0, 0, 0);

	mutex_unlock(&rdev->srbm_mutex);



	cik_pcie_init_compute_vmid(rdev);



	cik_pcie_gart_tlb_flush(rdev);

	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",

		 (unsigned)(rdev->mc.gtt_size >> 20),

drivers/gpu/drm/radeon/radeon_kfd.c

+0 −39
Original line number Diff line number Diff line
@@ -63,8 +63,6 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 
static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,

					unsigned int vmid);



static int kgd_init_memory(struct kgd_dev *kgd);



static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,

				uint32_t hpd_size, uint64_t hpd_gpu_addr);
@@ -89,7 +87,6 @@ static const struct kfd2kgd_calls kfd2kgd = { 
	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,

	.program_sh_mem_settings = kgd_program_sh_mem_settings,

	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,

	.init_memory = kgd_init_memory,

	.init_pipeline = kgd_init_pipeline,

	.hqd_load = kgd_hqd_load,

	.hqd_sdma_load = kgd_hqd_sdma_load,
@@ -375,42 +372,6 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 
	return 0;

}



static int kgd_init_memory(struct kgd_dev *kgd)

{

	/*

	 * Configure apertures:

	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)

	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)

	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)

	 */

	int i;

	uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);



	for (i = 8; i < 16; i++) {

		uint32_t sh_mem_config;



		lock_srbm(kgd, 0, 0, 0, i);



		sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);

		sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);



		write_register(kgd, SH_MEM_CONFIG, sh_mem_config);



		write_register(kgd, SH_MEM_BASES, sh_mem_bases);



		/* Scratch aperture is not supported for now. */

		write_register(kgd, SH_STATIC_MEM_CONFIG, 0);



		/* APE1 disabled for now. */

		write_register(kgd, SH_MEM_APE1_BASE, 1);

		write_register(kgd, SH_MEM_APE1_LIMIT, 0);



		unlock_srbm(kgd);

	}



	return 0;

}



static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,

				uint32_t hpd_size, uint64_t hpd_gpu_addr)

{