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Commit 08b16886 authored by Zeyu Fan's avatar Zeyu Fan Committed by Alex Deucher
Browse files

drm/amd/display: Move DCHUBBUB block from MemInput to HW sequencer. 



Signed-off-by: default avatarZeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: default avatarZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c8d7bd8b

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −3
Original line number Diff line number Diff line
@@ -2042,10 +2042,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) 
		return false;

	}



	if (mi->funcs->mem_input_update_dchub)

		mi->funcs->mem_input_update_dchub(mi, dh_data);

	if (core_dc->hwss.update_dchub)

		core_dc->hwss.update_dchub(core_dc->hwseq, dh_data);

	else

		ASSERT(mi->funcs->mem_input_update_dchub);

		ASSERT(core_dc->hwss.update_dchub);





	return true;

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+113 −9
Original line number Diff line number Diff line
@@ -116,6 +116,15 @@ 
	.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \

	.BLND_CONTROL[3] = mmBLNDV_CONTROL



#define HWSEQ_DCE120_REG_LIST() \

	HWSEQ_DCE10_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \

	HWSEQ_PHYPLL_REG_LIST(CRTC), \

	SR(DCHUB_FB_LOCATION),\

	SR(DCHUB_AGP_BASE),\

	SR(DCHUB_AGP_BOT),\

	SR(DCHUB_AGP_TOP)



#define HWSEQ_DCE112_REG_LIST() \

	HWSEQ_DCE10_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
@@ -146,8 +155,31 @@ 
	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \

	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \

	SR(REFCLK_CNTL), \

	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\

	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\

	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\

	SR(DCHUBBUB_ARB_SAT_LEVEL),\

	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\

	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \

	SR(DCHUBBUB_TEST_DEBUG_INDEX), \

	SR(DCHUBBUB_TEST_DEBUG_DATA), \

	SR(DC_IP_REQUEST_CNTL), \
@@ -180,7 +212,13 @@ 


#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define HWSEQ_DCN1_REG_LIST()\

	HWSEQ_DCN_REG_LIST()

	HWSEQ_DCN_REG_LIST(), \

	SR(DCHUBBUB_SDPIF_FB_TOP),\

	SR(DCHUBBUB_SDPIF_FB_BASE),\

	SR(DCHUBBUB_SDPIF_FB_OFFSET),\

	SR(DCHUBBUB_SDPIF_AGP_BASE),\

	SR(DCHUBBUB_SDPIF_AGP_BOT),\

	SR(DCHUBBUB_SDPIF_AGP_TOP)

#endif
@@ -194,6 +232,11 @@ struct dce_hwseq_registers { 
	uint32_t CRTC_H_BLANK_START_END[6];

	uint32_t PIXEL_RATE_CNTL[6];

	uint32_t PHYPLL_PIXEL_RATE_CNTL[6];

	/*DCHUB*/

	uint32_t DCHUB_FB_LOCATION;

	uint32_t DCHUB_AGP_BASE;

	uint32_t DCHUB_AGP_BOT;

	uint32_t DCHUB_AGP_TOP;



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	uint32_t OTG_GLOBAL_SYNC_STATUS[4];
@@ -202,10 +245,39 @@ struct dce_hwseq_registers { 
	uint32_t DPP_CONTROL[4];

	uint32_t OPP_PIPE_CONTROL[4];

	uint32_t REFCLK_CNTL;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;

	uint32_t DCHUBBUB_ARB_SAT_LEVEL;

	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;

	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;

	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;

	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;

	uint32_t DCHUBBUB_TEST_DEBUG_DATA;

	uint32_t DCHUBBUB_SDPIF_FB_TOP;

	uint32_t DCHUBBUB_SDPIF_FB_BASE;

	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;

	uint32_t DCHUBBUB_SDPIF_AGP_BASE;

	uint32_t DCHUBBUB_SDPIF_AGP_BOT;

	uint32_t DCHUBBUB_SDPIF_AGP_TOP;

	uint32_t DC_IP_REQUEST_CNTL;

	uint32_t DOMAIN0_PG_CONFIG;

	uint32_t DOMAIN1_PG_CONFIG;
@@ -300,11 +372,19 @@ struct dce_hwseq_registers { 
	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\

	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)



#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\

	SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\

	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\

	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\

	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\

	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)



#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\

	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)

	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
@@ -342,6 +422,12 @@ struct dce_hwseq_registers { 
	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \

	HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \

	HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)

#endif
@@ -349,6 +435,12 @@ struct dce_hwseq_registers { 
#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \

	HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \

	HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \

	HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)

#endif
@@ -370,7 +462,6 @@ struct dce_hwseq_registers { 
	type PHYPLL_PIXEL_RATE_SOURCE; \

	type PIXEL_RATE_PLL_SOURCE; \



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define HWSEQ_DCN_REG_FIELD_LIST(type) \

	type VUPDATE_NO_LOCK_EVENT_CLEAR; \

	type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
@@ -378,7 +469,25 @@ struct dce_hwseq_registers { 
	type HUBP_CLOCK_ENABLE; \

	type DPP_CLOCK_ENABLE; \

	type DPPCLK_RATE_CONTROL; \

	type SDPIF_FB_TOP;\

	type SDPIF_FB_BASE;\

	type SDPIF_FB_OFFSET;\

	type SDPIF_AGP_BASE;\

	type SDPIF_AGP_BOT;\

	type SDPIF_AGP_TOP;\

	type FB_TOP;\

	type FB_BASE;\

	type FB_OFFSET;\

	type AGP_BASE;\

	type AGP_BOT;\

	type AGP_TOP;\

	type DCHUBBUB_GLOBAL_TIMER_ENABLE; \

	type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\

	type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\

	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\

	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\

	type DCHUBBUB_ARB_SAT_LEVEL;\

	type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\

	type OPP_PIPE_CLOCK_EN;\

	type IP_REQUEST_EN; \

	type DOMAIN0_POWER_FORCEON; \
@@ -408,20 +517,15 @@ struct dce_hwseq_registers { 
	type DCFCLK_GATE_DIS; \

	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \

	type DENTIST_DPPCLK_WDIVIDER;

#endif



struct dce_hwseq_shift {

	HWSEQ_REG_FIELD_LIST(uint8_t)

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)

#endif

};



struct dce_hwseq_mask {

	HWSEQ_REG_FIELD_LIST(uint32_t)

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	HWSEQ_DCN_REG_FIELD_LIST(uint32_t)

#endif

};

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

+1 −53
Original line number Diff line number Diff line
@@ -656,57 +656,6 @@ static bool dce_mi_program_surface_flip_and_addr( 
	return true;

}



static void dce_mi_update_dchub(struct mem_input *mi,

		struct dchub_init_data *dh_data)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	/* TODO: port code from dal2 */

	switch (dh_data->fb_mode) {

	case FRAME_BUFFER_MODE_ZFB_ONLY:

		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/

		REG_UPDATE_2(DCHUB_FB_LOCATION,

				FB_TOP, 0,

				FB_BASE, 0x0FFFF);



		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_LOCAL_ONLY:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, 0);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, 0x03FFFF);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, 0);

		break;

	default:

		break;

	}



	dh_data->dchub_initialzied = true;

	dh_data->dchub_info_valid = false;

}



static struct mem_input_funcs dce_mi_funcs = {

	.mem_input_program_display_marks = dce_mi_program_display_marks,

	.allocate_mem_input = dce_mi_allocate_dmif,
@@ -716,8 +665,7 @@ static struct mem_input_funcs dce_mi_funcs = { 
	.mem_input_program_pte_vm = dce_mi_program_pte_vm,

	.mem_input_program_surface_config =

			dce_mi_program_surface_config,

	.mem_input_is_flip_pending = dce_mi_is_flip_pending,

	.mem_input_update_dchub = dce_mi_update_dchub

	.mem_input_is_flip_pending = dce_mi_is_flip_pending

};

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#include "abm.h"

#include "audio.h"

#include "dce/dce_hwseq.h"

#include "reg_helper.h"



/* include DCE11 register header files */

#include "dce/dce_11_0_d.h"

drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

+64 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "core_dc.h"

#include "core_types.h"

#include "dce120_hw_sequencer.h"

#include "dce/dce_hwseq.h"



#include "dce110/dce110_hw_sequencer.h"
@@ -37,6 +38,15 @@ 
#include "vega10/soc15ip.h"

#include "reg_helper.h"



#define CTX \

	hws->ctx

#define REG(reg)\

	hws->regs->reg



#undef FN

#define FN(reg_name, field_name) \

	hws->shifts->field_name, hws->masks->field_name



struct dce120_hw_seq_reg_offsets {

	uint32_t crtc;

};
@@ -184,6 +194,59 @@ static bool dce120_enable_display_power_gating( 
	return false;

}



static void dce120_update_dchub(

	struct dce_hwseq *hws,

	struct dchub_init_data *dh_data)

{

	/* TODO: port code from dal2 */

	switch (dh_data->fb_mode) {

	case FRAME_BUFFER_MODE_ZFB_ONLY:

		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/

		REG_UPDATE_2(DCHUB_FB_LOCATION,

				FB_TOP, 0,

				FB_BASE, 0x0FFFF);



		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_LOCAL_ONLY:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, 0);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, 0x03FFFF);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, 0);

		break;

	default:

		break;

	}



	dh_data->dchub_initialzied = true;

	dh_data->dchub_info_valid = false;

}







bool dce120_hw_sequencer_construct(struct core_dc *dc)

{

	/* All registers used by dce11.2 match those in dce11 in offset and
@@ -191,6 +254,7 @@ bool dce120_hw_sequencer_construct(struct core_dc *dc) 
	 */

	dce110_hw_sequencer_construct(dc);

	dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;

	dc->hwss.update_dchub = dce120_update_dchub;



	return true;

}