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Commit 089c6fd5 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Update cached cdclk state from broxton_init_cdclk() 



Let's make sure our cached cdclk state is accurate right after
broxton_init_cdclk() whether or not we end up changing the cdclk
frequency.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-18-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent 83d7c81f

drivers/gpu/drm/i915/intel_display.c

+3 −6
Original line number Original line Diff line number Diff line
@@ -5428,13 +5428,10 @@ bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv) 




void broxton_init_cdclk(struct drm_i915_private *dev_priv)

void broxton_init_cdclk(struct drm_i915_private *dev_priv)

{

{

	/* check if cd clock is enabled */

	intel_update_cdclk(dev_priv->dev);

	if (broxton_cdclk_is_enabled(dev_priv)) {

		DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");

		return;

	}





	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");

	if (dev_priv->cdclk_pll.vco != 0)

		return;





	/*

	/*

	 * FIXME:

	 * FIXME: