Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0890a264 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC architecture updates from Vineet Gupta:

 - support for HS38 cores based on ARCv2 ISA

     ARCv2 is the next generation ISA from Synopsys and basis for the
     HS3{4,6,8} families of processors which retain the traditional ARC mantra of
     low power and configurability and are now more performant and feature rich.

     HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
     SMP (upto 4 cores) among other features.

     + www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
     + http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
     + http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps

 - support for ARC SDP (Software Development platform): Main Board + CPU Cards
    = AXS101: CPU Card with ARC700 in silicon @ 700 MHz
    = AXS103: CPU Card with HS38x in FPGA

 - refactoring of ARCompact port to accomodate new ARCv2 ISA

 - misc updates/cleanups

* tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)
  ARC: Fix build failures for ARCompact in linux-next after ARCv2 support
  ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support
  ARCv2: [vdk] dts files and defconfig for HS38 VDK
  ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
  ARC: [axs101] Prepare for AXS103
  ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores
  ARCv2: All bits in place, allow ARCv2 builds
  ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
  ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
  ARC: Reduce bitops lines of code using macros
  ARCv2: barriers
  arch: conditionally define smp_{mb,rmb,wmb}
  ARC: add smp barriers around atomics per Documentation/atomic_ops.txt
  ARC: add compiler barrier to LLSC based cmpxchg
  ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
  ARCv2: SMP: clocksource: Enable Global Real Time counter
  ARCv2: SMP: ARConnect debug/robustness
  ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al
  ARC: make plat_smp_ops weak to allow over-rides
  ARCv2: clocksource: Introduce 64bit local RTC counter
  ...
parents 05a8256c 40b8ad8f

Documentation/devicetree/bindings/arc/archs-idu-intc.txt

0 → 100644
+46 −0
Original line number Diff line number Diff line 
* ARC-HS Interrupt Distribution Unit



  This optional 2nd level interrupt controller can be used in SMP configurations for

  dynamic IRQ routing, load balancing of common/external IRQs towards core intc.



Properties:



- compatible: "snps,archs-idu-intc"

- interrupt-controller: This is an interrupt controller.

- interrupt-parent: <reference to parent core intc>

- #interrupt-cells: Must be <2>.

- interrupts: <...> specifies the upstream core irqs



  First cell specifies the "common" IRQ from peripheral to IDU

  Second cell specifies the irq distribution mode to cores

     0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.



Example:

	core_intc: core-interrupt-controller {

		compatible = "snps,archs-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

	};



	idu_intc: idu-interrupt-controller {

		compatible = "snps,archs-idu-intc";

		interrupt-controller;

		interrupt-parent = <&core_intc>;



		/*

		 * <hwirq  distribution>

		 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

		 */

		#interrupt-cells = <2>;



		/* upstream core irqs: downstream these are "COMMON" irq 0,1..  */

		interrupts = <24 25 26 27 28 29 30 31>;

	};



	some_device: serial@c0fc1000 {

		interrupt-parent = <&idu_intc>;

		interrupts = <0 0>;	/* upstream idu IRQ #24, Round Robin */

	};

Documentation/devicetree/bindings/arc/archs-intc.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)



Properties:



- compatible: "snps,archs-intc"

- interrupt-controller: This is an interrupt controller.

- #interrupt-cells: Must be <1>.



  Single Cell "interrupts" property of a device specifies the IRQ number

  between 16 to 256



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.



Example:



	intc: interrupt-controller {

		compatible = "snps,archs-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupts = <16 17 18 19 20 21 22 23 24 25>;

	};

Documentation/devicetree/bindings/arc/axs101.txt

0 → 100644
+7 −0
Original line number Diff line number Diff line 
Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings

---------------------------------------------------------------------------



SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon



Required root node properties:

    - compatible = "snps,axs101", "snps,arc-sdp";

Documentation/devicetree/bindings/arc/axs103.txt

0 → 100644
+8 −0
Original line number Diff line number Diff line 
Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings

---------------------------------------------------------------------------



SDP Main Board with an AXC003 FPGA Card which can contain various flavours of

HS38x cores.



Required root node properties:

    - compatible = "snps,axs103", "snps,arc-sdp";

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -9832,6 +9832,13 @@ F: arch/arc/ 
F:	Documentation/devicetree/bindings/arc/

F:	drivers/tty/serial/arc_uart.c



SYNOPSYS ARC SDP platform support

M:	Alexey Brodkin <abrodkin@synopsys.com>

S:	Supported

F:	arch/arc/plat-axs10x

F:	arch/arc/boot/dts/ax*

F:	Documentation/devicetree/bindings/arc/axs10*



SYSTEM CONFIGURATION (SYSCON)

M:	Lee Jones <lee.jones@linaro.org>

M:	Arnd Bergmann <arnd@arndb.de>