Blackfin arch: Add header files for BF548

/*

 * File:         include/asm-blackfin/mach-bf548/anomaly.h

 * Based on:

 * Author:

 *

 * Created:

 * Description:

 *

 * Rev:

 *

 * Modified:

 *

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; see the file COPYING.

 * If not, write to the Free Software Foundation,

 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

 */

#ifndef _MACH_ANOMALY_H_

#define _MACH_ANOMALY_H_

#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in

			    slot1 and store of a P register in slot 2 is not

			    supported */

#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive

			    Channel DMA stops */

#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR

			    registers. */

#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the

			    Shadow of a Conditional Branch */

#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event

			    interrupt not functional */

#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on

			    SPORT external receive and transmit clocks. */

#define ANOMALY_05000272 /* Certain data cache write through modes fail for

			    VDDint <=0.9V */

#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the

			    Boundary of Reserved Memory */

#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and

			    LC Registers Are Interrupted */

#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */

#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */

#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to

			    the USB FIFO Simultaneously */

#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()

			    function */

#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional

			    */

#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */

#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM

			    Skew */

#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */

#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration

			    of Host DMA Port */

#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent

			    Allowed Configuration on Host DMA Port */

#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */

#endif /* _MACH_ANOMALY_H_ */

/*

 * File:         include/asm-blackfin/mach-bf548/bf548.h

 * Based on:

 * Author:

 *

 * Created:

 * Description:  System MMR register and memory map for ADSP-BF548

 *

 * Modified:

 *               Copyright 2004-2007 Analog Devices Inc.

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see the file COPYING, or write

 * to the Free Software Foundation, Inc.,

 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */

#ifndef __MACH_BF548_H__

#define __MACH_BF548_H__

/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */

#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)	/* SPI_STAT */

#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)	/* SPORTx_STAT */

#define PPI_ERR_MASK (0xFFFF & ~FLD)	/* PPI_STATUS */

#define UART_ERR_MASK_STAT1 (0x4)	/* UARTx_IIR */

#define UART_ERR_MASK_STAT0 (0x2)	/* UARTx_IIR */

#define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \

		RMLIF | UCEIF | EXTIF | ADIF)	/* CAN_GIF */

#define OFFSET_(x) ((x) & 0x0000FFFF)

/*some misc defines*/

#define IMASK_IVG15		0x8000

#define IMASK_IVG14		0x4000

#define IMASK_IVG13		0x2000

#define IMASK_IVG12		0x1000

#define IMASK_IVG11		0x0800

#define IMASK_IVG10		0x0400

#define IMASK_IVG9		0x0200

#define IMASK_IVG8		0x0100

#define IMASK_IVG7		0x0080

#define IMASK_IVGTMR	0x0040

#define IMASK_IVGHW		0x0020

/***************************/

#define BLKFIN_DSUBBANKS	4

#define BLKFIN_DWAYS		2

#define BLKFIN_DLINES		64

#define BLKFIN_ISUBBANKS	4

#define BLKFIN_IWAYS		4

#define BLKFIN_ILINES		32

#define WAY0_L			0x1

#define WAY1_L			0x2

#define WAY01_L			0x3

#define WAY2_L			0x4

#define WAY02_L			0x5

#define	WAY12_L			0x6

#define	WAY012_L		0x7

#define	WAY3_L			0x8

#define	WAY03_L			0x9

#define	WAY13_L			0xA

#define	WAY013_L		0xB

#define	WAY32_L			0xC

#define	WAY320_L		0xD

#define	WAY321_L		0xE

#define	WAYALL_L		0xF

#define DMC_ENABLE (2<<2)	/*yes, 2, not 1 */

/********************************* EBIU Settings ************************************/

#define AMBCTL0VAL	((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)

#define AMBCTL1VAL	((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)

#ifdef CONFIG_C_AMBEN_ALL

#define V_AMBEN AMBEN_ALL

#endif

#ifdef CONFIG_C_AMBEN

#define V_AMBEN 0x0

#endif

#ifdef CONFIG_C_AMBEN_B0

#define V_AMBEN AMBEN_B0

#endif

#ifdef CONFIG_C_AMBEN_B0_B1

#define V_AMBEN AMBEN_B0_B1

#endif

#ifdef CONFIG_C_AMBEN_B0_B1_B2

#define V_AMBEN AMBEN_B0_B1_B2

#endif

#ifdef CONFIG_C_AMCKEN

#define V_AMCKEN AMCKEN

#else

#define V_AMCKEN 0x0

#endif

#ifdef CONFIG_C_CDPRIO

#define V_CDPRIO 0x100

#else

#define V_CDPRIO 0x0

#endif

#define AMGCTLVAL	(V_AMBEN | V_AMCKEN | V_CDPRIO)

#define MAX_VC	650000000

#define MIN_VC	50000000

/********************************PLL Settings **************************************/

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#if (CONFIG_VCO_MULT < 0)

#error "VCO Multiplier is less than 0. Please select a different value"

#endif

#if (CONFIG_VCO_MULT == 0)

#error "VCO Multiplier should be greater than 0. Please select a different value"

#endif

#if (CONFIG_VCO_MULT > 64)

#error "VCO Multiplier is more than 64. Please select a different value"

#endif

#ifndef CONFIG_CLKIN_HALF

#define CONFIG_VCO_HZ	(CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)

#else

#define CONFIG_VCO_HZ	((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)

#endif

#ifndef CONFIG_PLL_BYPASS

#define CONFIG_CCLK_HZ	(CONFIG_VCO_HZ/CONFIG_CCLK_DIV)

#define CONFIG_SCLK_HZ	(CONFIG_VCO_HZ/CONFIG_SCLK_DIV)

#else

#define CONFIG_CCLK_HZ	CONFIG_CLKIN_HZ

#define CONFIG_SCLK_HZ	CONFIG_CLKIN_HZ

#endif

#if (CONFIG_SCLK_DIV < 1)

#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"

#endif

#if (CONFIG_SCLK_DIV > 15)

#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"

#endif

#if (CONFIG_CCLK_DIV != 1)

#if (CONFIG_CCLK_DIV != 2)

#if (CONFIG_CCLK_DIV != 4)

#if (CONFIG_CCLK_DIV != 8)

#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"

#endif

#endif

#endif

#endif

#if (CONFIG_VCO_HZ > MAX_VC)

#error "VCO selected is more than maximum value. Please change the VCO multipler"

#endif

#if (CONFIG_SCLK_HZ > 133000000)

#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"

#endif

#if (CONFIG_SCLK_HZ < 27000000)

#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"

#endif

#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)

#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)

#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)

#error "Please select sclk less than cclk"

#endif

#endif

#endif

#if (CONFIG_CCLK_DIV == 1)

#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1

#endif

#if (CONFIG_CCLK_DIV == 2)

#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2

#endif

#if (CONFIG_CCLK_DIV == 4)

#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4

#endif

#if (CONFIG_CCLK_DIV == 8)

#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8

#endif

#ifndef CONFIG_CCLK_ACT_DIV

#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly

#endif

#endif	/* CONFIG_BFIN_KERNEL_CLOCK */

#ifdef CONFIG_BF542

#define CPU "BF542"

#define CPUID 0x027c8000

#endif

#ifdef CONFIG_BF544

#define CPU "BF544"

#define CPUID 0x027c8000

#endif

#ifdef CONFIG_BF548

#define CPU "BF548"

#define CPUID 0x027c6000

#endif

#ifdef CONFIG_BF549

#define CPU "BF549"

#endif

#ifndef CPU

#define	CPU "UNKNOWN"

#define CPUID 0x0

#endif

#if (CONFIG_MEM_SIZE % 4)

#error "SDRAM mem size must be multible of 4MB"

#endif

#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)

#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)

#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)

#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)

/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/

#define ANOMALY_05000158_WORKAROUND		0x200

#ifdef CONFIG_BLKFIN_WB		/*Write Back Policy */

#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \

			| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)

#else				/*Write Through */

#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \

			| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )

#endif

#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )

#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )

#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )

#define SDRAM_OOPS  	 (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )

#define SIZE_1K 0x00000400	/* 1K */

#define SIZE_4K 0x00001000	/* 4K */

#define SIZE_1M 0x00100000	/* 1M */

#define SIZE_4M 0x00400000	/* 4M */

#define MAX_CPLBS (16 * 2)

/*

* Number of required data CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 16 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Data Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

* 1 for ASYNC Memory

*/

#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)

/*

* Number of required instruction CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 12 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Instruction Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

*/

#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)

#endif	/* __MACH_BF48_H__  */

#include <linux/serial.h>

#include <asm/dma.h>

#define NR_PORTS		2

#define OFFSET_THR              0x00	/* Transmit Holding register            */

#define OFFSET_RBR              0x00	/* Receive Buffer register              */

#define OFFSET_DLL              0x00	/* Divisor Latch (Low-Byte)             */

#define OFFSET_IER              0x04	/* Interrupt Enable Register            */

#define OFFSET_DLH              0x04	/* Divisor Latch (High-Byte)            */

#define OFFSET_IIR              0x08	/* Interrupt Identification Register    */

#define OFFSET_LCR              0x0C	/* Line Control Register                */

#define OFFSET_MCR              0x10	/* Modem Control Register               */

#define OFFSET_LSR              0x14	/* Line Status Register                 */

#define OFFSET_MSR              0x18	/* Modem Status Register                */

#define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */

#define OFFSET_GCTL             0x24	/* Global Control Register              */

#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))

#define UART_GET_DLL(uart)	bfin_read16(((uart)->port.membase + OFFSET_DLL))

#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))

#define UART_GET_DLH(uart)	bfin_read16(((uart)->port.membase + OFFSET_DLH))

#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))

#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))

#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))

#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))

#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)

#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)

#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)

#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)

#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)

#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)

#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)

# define CONFIG_SERIAL_BFIN_CTSRTS

# ifndef CONFIG_UART0_CTS_PIN

#  define CONFIG_UART0_CTS_PIN -1

# endif

# ifndef CONFIG_UART0_RTS_PIN

#  define CONFIG_UART0_RTS_PIN -1

# endif

# ifndef CONFIG_UART1_CTS_PIN

#  define CONFIG_UART1_CTS_PIN -1

# endif

# ifndef CONFIG_UART1_RTS_PIN

#  define CONFIG_UART1_RTS_PIN -1

# endif

#endif

/*

 * The pin configuration is different from schematic

 */

struct bfin_serial_port {

        struct uart_port        port;

        unsigned int            old_status;

#ifdef CONFIG_SERIAL_BFIN_DMA

	int			tx_done;

	int			tx_count;

	struct circ_buf		rx_dma_buf;

	struct timer_list       rx_dma_timer;

	int			rx_dma_nrows;

	unsigned int		tx_dma_channel;

	unsigned int		rx_dma_channel;

	struct work_struct	tx_dma_workqueue;

#else

	struct work_struct 	cts_workqueue;

#endif

#ifdef CONFIG_SERIAL_BFIN_CTSRTS

	int		cts_pin;

	int 		rts_pin;

#endif

};

struct bfin_serial_port bfin_serial_ports[NR_PORTS];

struct bfin_serial_res {

	unsigned long	uart_base_addr;

	int		uart_irq;

#ifdef CONFIG_SERIAL_BFIN_DMA

	unsigned int	uart_tx_dma_channel;

	unsigned int	uart_rx_dma_channel;

#endif

#ifdef CONFIG_SERIAL_BFIN_CTSRTS

	int	uart_cts_pin;

	int	uart_rts_pin;

#endif

};

struct bfin_serial_res bfin_serial_resource[] = {

#ifdef CONFIG_SERIAL_BFIN_UART0

	{

	0xFFC00400,

	IRQ_UART0_RX,

#ifdef CONFIG_SERIAL_BFIN_DMA

	CH_UART0_TX,

	CH_UART0_RX,

#endif

#ifdef CONFIG_BFIN_UART0_CTSRTS

	CONFIG_UART0_CTS_PIN,

	CONFIG_UART0_RTS_PIN,

#endif

	},

#endif

#ifdef CONFIG_SERIAL_BFIN_UART1

	{

	0xFFC02000,

	IRQ_UART1_RX,

#ifdef CONFIG_SERIAL_BFIN_DMA

	CH_UART1_TX,

	CH_UART1_RX,

#endif

#ifdef CONFIG_BFIN_UART1_CTSRTS

	CONFIG_UART1_CTS_PIN,

	CONFIG_UART1_RTS_PIN,

#endif

	},

#endif

};

int nr_ports = ARRAY_SIZE(bfin_serial_resource);

static void bfin_serial_hw_init(struct bfin_serial_port *uart)

{

	unsigned short val;

	val = bfin_read16(BFIN_PORT_MUX);

	val &= ~(PFDE | PFTE);

	bfin_write16(BFIN_PORT_MUX, val);

	val = bfin_read16(PORTF_FER);

	val |= 0xF;

	bfin_write16(PORTF_FER, val);

#ifdef CONFIG_SERIAL_BFIN_CTSRTS

	if (uart->cts_pin >= 0) {

		gpio_request(uart->cts_pin, NULL);

		gpio_direction_input(uart->cts_pin);

	}

	if (uart->rts_pin >= 0) {

		gpio_request(uart->rts_pin, NULL);

		gpio_direction_output(uart->rts_pin);

	}

#endif

}

/*

 * File:         include/asm-blackfin/mach-bf548/blackfin.h

 * Based on:

 * Author:

 *

 * Created:

 * Description:

 *

 * Rev:

 *

 * Modified:

 *

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; see the file COPYING.

 * If not, write to the Free Software Foundation,

 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

 */

#ifndef _MACH_BLACKFIN_H_

#define _MACH_BLACKFIN_H_

#define BF548_FAMILY

#ifdef CONFIG_BF542

#include "bf542.h"

#ifdef CONFIG_BF544

#include "bf544.h"

#endif

#ifdef CONFIG_BF548

#include "bf548.h"

#endif

#ifdef CONFIG_BF549

#include "bf549.h"

#endif

#include "mem_map.h"

#include "anomaly.h"

#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))

#ifdef CONFIG_BF542

#include "cdefBF542.h"

#endif

#ifdef CONFIG_BF544

#include "cdefBF544.h"

#endif

#ifdef CONFIG_BF548

#include "cdefBF548.h"

#endif

#ifdef CONFIG_BF549

#include "cdefBF549.h"

#endif

/* UART 1*/

#define bfin_read_UART_THR()		bfin_read_UART1_THR()

#define bfin_write_UART_THR(val)	bfin_write_UART1_THR(val)

#define bfin_read_UART_RBR()		bfin_read_UART1_RBR()

#define bfin_write_UART_RBR(val)	bfin_write_UART1_RBR(val)

#define bfin_read_UART_DLL()		bfin_read_UART1_DLL()

#define bfin_write_UART_DLL(val)	bfin_write_UART1_DLL(val)

#define bfin_read_UART_IER()		bfin_read_UART1_IER()

#define bfin_write_UART_IER(val)	bfin_write_UART1_IER(val)

#define bfin_read_UART_DLH()		bfin_read_UART1_DLH()

#define bfin_write_UART_DLH(val)	bfin_write_UART1_DLH(val)

#define bfin_read_UART_IIR()		bfin_read_UART1_IIR()

#define bfin_write_UART_IIR(val)	bfin_write_UART1_IIR(val)

#define bfin_read_UART_LCR()		bfin_read_UART1_LCR()

#define bfin_write_UART_LCR(val)	bfin_write_UART1_LCR(val)

#define bfin_read_UART_MCR()		bfin_read_UART1_MCR()

#define bfin_write_UART_MCR(val)	bfin_write_UART1_MCR(val)

#define bfin_read_UART_LSR()		bfin_read_UART1_LSR()

#define bfin_write_UART_LSR(val)	bfin_write_UART1_LSR(val)

#define bfin_read_UART_SCR()		bfin_read_UART1_SCR()

#define bfin_write_UART_SCR(val)	bfin_write_UART1_SCR(val)

#define bfin_read_UART_GCTL()		bfin_read_UART1_GCTL()

#define bfin_write_UART_GCTL(val)	bfin_write_UART1_GCTL(val)

#endif

/* MAP used DEFINES from BF533 to BF54x - so we don't need to change 

 * them in the driver, kernel, etc. */

/* UART_IIR Register */

#define STATUS(x)	((x << 1) & 0x06)

#define STATUS_P1	0x02

#define STATUS_P0	0x01

/* UART 0*/

/* DMA Channnel */

#define bfin_read_CH_UART_RX()		bfin_read_CH_UART1_RX()

#define bfin_write_CH_UART_RX(val)	bfin_write_CH_UART1_RX(val)

#define bfin_read_CH_UART_TX()		bfin_read_CH_UART1_TX()

#define bfin_write_CH_UART_TX(val)	bfin_write_CH_UART1_TX(val)

#define CH_UART_RX			CH_UART1_RX

#define CH_UART_TX			CH_UART1_TX

/* System Interrupt Controller */

#define bfin_read_IRQ_UART_RX()		bfin_read_IRQ_UART1_RX()

#define bfin_write_IRQ_UART_RX(val)	bfin_write_IRQ_UART1_RX(val)

#define bfin_read_IRQ_UART_TX()		bfin_read_IRQ_UART1_TX()

#define bfin_write_IRQ_UART_TX(val)	bfin_write_IRQ_UART1_TX(val)

#define bfin_read_IRQ_UART_ERROR()	bfin_read_IRQ_UART1_ERROR()

#define bfin_write_IRQ_UART_ERROR(val)	bfin_write_IRQ_UART1_ERROR(val)

#define IRQ_UART_RX			IRQ_UART1_RX

#define	IRQ_UART_TX			IRQ_UART1_TX

#define	IRQ_UART_ERROR			IRQ_UART1_ERROR

/* MMR Registers*/

#define bfin_read_UART_THR()		bfin_read_UART1_THR()

#define bfin_write_UART_THR(val)	bfin_write_UART1_THR(val)

#define bfin_read_UART_RBR()		bfin_read_UART1_RBR()

#define bfin_write_UART_RBR(val)	bfin_write_UART1_RBR(val)

#define bfin_read_UART_DLL()		bfin_read_UART1_DLL()

#define bfin_write_UART_DLL(val)	bfin_write_UART1_DLL(val)

#define bfin_read_UART_IER()		bfin_read_UART1_IER()

#define bfin_write_UART_IER(val)	bfin_write_UART1_IER(val)

#define bfin_read_UART_DLH()		bfin_read_UART1_DLH()

#define bfin_write_UART_DLH(val)	bfin_write_UART1_DLH(val)

#define bfin_read_UART_IIR()		bfin_read_UART1_IIR()

#define bfin_write_UART_IIR(val)	bfin_write_UART1_IIR(val)

#define bfin_read_UART_LCR()		bfin_read_UART1_LCR()

#define bfin_write_UART_LCR(val)	bfin_write_UART1_LCR(val)

#define bfin_read_UART_MCR()		bfin_read_UART1_MCR()

#define bfin_write_UART_MCR(val)	bfin_write_UART1_MCR(val)

#define bfin_read_UART_LSR()		bfin_read_UART1_LSR()

#define bfin_write_UART_LSR(val)	bfin_write_UART1_LSR(val)

#define bfin_read_UART_SCR()		bfin_read_UART1_SCR()

#define bfin_write_UART_SCR(val)	bfin_write_UART1_SCR(val)

#define bfin_read_UART_GCTL()		bfin_read_UART1_GCTL()

#define bfin_write_UART_GCTL(val)	bfin_write_UART1_GCTL(val)

#define UART_THR			UART1_THR

#define UART_RBR			UART1_RBR

#define UART_DLL			UART1_DLL

#define UART_IER			UART1_IER

#define UART_DLH			UART1_DLH

#define UART_IIR			UART1_IIR

#define UART_LCR			UART1_LCR

#define UART_MCR			UART1_MCR

#define UART_LSR			UART1_LSR

#define UART_SCR			UART1_SCR

#define UART_GCTL			UART1_GCTL

/* PLL_DIV Masks */

#define CCLK_DIV1 CSEL_DIV1	/* CCLK = VCO / 1 */

#define CCLK_DIV2 CSEL_DIV2	/* CCLK = VCO / 2 */

#define CCLK_DIV4 CSEL_DIV4	/* CCLK = VCO / 4 */

#define CCLK_DIV8 CSEL_DIV8	/* CCLK = VCO / 8 */

#endif

/*

 * file:         include/asm-blackfin/mach-bf548/dma.h

 * based on:

 * author:

 *

 * created:

 * description:

 *	system mmr register map

 * rev:

 *

 * modified:

 *

 *

 * bugs:         enter bugs at http://blackfin.uclinux.org/

 *

 * this program is free software; you can redistribute it and/or modify

 * it under the terms of the gnu general public license as published by

 * the free software foundation; either version 2, or (at your option)

 * any later version.

 *

 * this program is distributed in the hope that it will be useful,

 * but without any warranty; without even the implied warranty of

 * merchantability or fitness for a particular purpose.  see the

 * gnu general public license for more details.

 *

 * you should have received a copy of the gnu general public license

 * along with this program; see the file copying.

 * if not, write to the free software foundation,

 * 59 temple place - suite 330, boston, ma 02111-1307, usa.

 */

#ifndef _MACH_DMA_H_

#define _MACH_DMA_H_

#define CH_SPORT0_RX		0

#define CH_SPORT0_TX		1

#define CH_SPORT1_RX		2

#define CH_SPORT1_TX		3

#define CH_SPI0			4

#define CH_SPI1			5

#define CH_UART0_RX 		6

#define CH_UART0_TX 		7

#define CH_UART1_RX 		8

#define CH_UART1_TX 		9

#define CH_ATAPI_RX		10

#define CH_ATAPI_TX		11

#define CH_EPPI0		12

#define CH_EPPI1		13

#define CH_EPPI2		14

#define CH_PIXC_IMAGE		15

#define CH_PIXC_OVERLAY		16

#define CH_PIXC_OUTPUT		17

#define CH_SPORT2_RX		18

#define CH_SPORT2_TX		19

#define CH_SPORT3_RX		20

#define CH_SPORT3_TX		21

#define CH_SDH			22

#define CH_SPI2			23

#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2

#endif