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Commit 085dd64e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-soc-3.20' of... 

Merge tag 'imx-soc-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "ARM: imx: soc changes for 3.20" from Shawn Guo:

The i.MX SoC changes for 3.20:
 - Add .disable_unused function hook for shared gate clock to ensure
   the clock tree use count matches the hardware state
 - Add a deeper idle state for i.MX6SX cpuidle driver powering off the
   ARM core
 - One correction on i.MX6Q esai_ipg parent clock setting
 - Add a missing iounmap call for imx6q_opp_check_speed_grading()
 - Add missing clocks for VF610 UART4, UART5 and SNVS blocks
 - Expand VF610 device tree compatible matching table to cover more
   Vybrid family SoCs
 - Expand i.MX clk-pllv3 a bit with the shift for frequency multiplier
   to support Vybrid's USB PLL oddity

* tag 'imx-soc-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  ARM: clk-imx6q: refine esai_ipg's parent
  ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()
  ARM: imx: clk-vf610: Add clock for SNVS
  ARM: imx: clk-vf610: Add clock for UART4 and UART5
  ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sx
  ARM: imx: support arm power off in cpuidle for i.mx6sx
  ARM: imx: remove unnecessary setting for DSM
  ARM: imx: correct the hardware clock gate setting for shared nodes
  ARM: imx: pllv3: add shift for frequency multiplier
  ARM vf610: add compatibilty strings of supported Vybrid SoC's

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents eeec0434 ade9233f

Documentation/devicetree/bindings/arm/fsl.txt

+12 −0
Original line number Diff line number Diff line
@@ -75,6 +75,18 @@ i.MX6q generic board 
Required root node properties:

    - compatible = "fsl,imx6q";



Freescale Vybrid Platform Device Tree Bindings

----------------------------------------------



For the Vybrid SoC familiy all variants with DDR controller are supported,

which is the VF5xx and VF6xx series. Out of historical reasons, in most

places the kernel uses vf610 to refer to the whole familiy.



Required root node compatible property (one of them):

    - compatible = "fsl,vf500";

    - compatible = "fsl,vf510";

    - compatible = "fsl,vf600";

    - compatible = "fsl,vf610";



Freescale LS1021A Platform Device Tree Bindings

------------------------------------------------

arch/arm/mach-imx/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y) 
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o

obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o

# i.MX6SX reuses i.MX6Q cpuidle driver

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o

endif



ifdef CONFIG_SND_IMX_SOC

arch/arm/mach-imx/clk-gate2.c

+19 −4
Original line number Diff line number Diff line
@@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) 
{

	struct clk_gate2 *gate = to_clk_gate2(hw);



	if (gate->share_count)

		return !!__clk_get_enable_count(hw->clk);

	else

	return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);

}



static void clk_gate2_disable_unused(struct clk_hw *hw)

{

	struct clk_gate2 *gate = to_clk_gate2(hw);

	unsigned long flags = 0;

	u32 reg;



	spin_lock_irqsave(gate->lock, flags);



	if (!gate->share_count || *gate->share_count == 0) {

		reg = readl(gate->reg);

		reg &= ~(3 << gate->bit_idx);

		writel(reg, gate->reg);

	}



	spin_unlock_irqrestore(gate->lock, flags);

}



static struct clk_ops clk_gate2_ops = {

	.enable = clk_gate2_enable,

	.disable = clk_gate2_disable,

	.disable_unused = clk_gate2_disable_unused,

	.is_enabled = clk_gate2_is_enabled,

};

arch/arm/mach-imx/clk-imx6q.c

+1 −1
Original line number Diff line number Diff line
@@ -386,7 +386,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);

	clk[IMX6QDL_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);

	clk[IMX6QDL_CLK_ESAI_EXTAL]   = imx_clk_gate2_shared("esai_extal",   "esai_podf",   base + 0x6c, 16, &share_count_esai);

	clk[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ipg",           base + 0x6c, 16, &share_count_esai);

	clk[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);

	clk[IMX6QDL_CLK_ESAI_MEM]     = imx_clk_gate2_shared("esai_mem", "ahb",             base + 0x6c, 16, &share_count_esai);

	clk[IMX6QDL_CLK_GPT_IPG]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);

	clk[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);

arch/arm/mach-imx/clk-pllv3.c

+7 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
 * @base:	 base address of PLL registers

 * @powerup_set: set POWER bit to power up the PLL

 * @div_mask:	 mask of divider bits

 * @div_shift:	 shift of divider bits

 *

 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3

 * is actually a multiplier, and always sits at bit 0.
@@ -40,6 +41,7 @@ struct clk_pllv3 { 
	void __iomem	*base;

	bool		powerup_set;

	u32		div_mask;

	u32		div_shift;

};



#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 
					   unsigned long parent_rate)

{

	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	u32 div = readl_relaxed(pll->base)  & pll->div_mask;

	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;



	return (div == 1) ? parent_rate * 22 : parent_rate * 20;

}
@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 
		return -EINVAL;



	val = readl_relaxed(pll->base);

	val &= ~pll->div_mask;

	val |= div;

	val &= ~(pll->div_mask << pll->div_shift);

	val |= (div << pll->div_shift);

	writel_relaxed(val, pll->base);



	return clk_pllv3_wait_lock(pll);
@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
	case IMX_PLLV3_SYS:

		ops = &clk_pllv3_sys_ops;

		break;

	case IMX_PLLV3_USB_VF610:

		pll->div_shift = 1;

	case IMX_PLLV3_USB:

		ops = &clk_pllv3_ops;

		pll->powerup_set = true;