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Commit 071bfefd authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville
Browse files

ath9k_hw: fix calculated runtime tx power limit



Use the previously calculated maximum of all rates instead of just the one
from the lowest rate of the selected PHY mode.

Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent e832bf10
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+1 −19
Original line number Original line Diff line number Diff line
@@ -4922,25 +4922,7 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
			"TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
			"TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
	}
	}


	/*
	ah->txpower_limit = regulatory->max_power_level;
	 * This is the TX power we send back to driver core,
	 * and it can use to pass to userspace to display our
	 * currently configured TX power setting.
	 *
	 * Since power is rate dependent, use one of the indices
	 * from the AR9300_Rates enum to select an entry from
	 * targetPowerValT2[] to report. Currently returns the
	 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
	 * as CCK power is less interesting (?).
	 */
	i = ALL_TARGET_LEGACY_6_24; /* legacy */
	if (IS_CHAN_HT40(chan))
		i = ALL_TARGET_HT40_0_8_16; /* ht40 */
	else if (IS_CHAN_HT20(chan))
		i = ALL_TARGET_HT20_0_8_16; /* ht20 */

	ah->txpower_limit = targetPowerValT2[i];
	regulatory->max_power_level = targetPowerValT2[i];


	/* Write target power array to registers */
	/* Write target power array to registers */
	ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
	ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
+0 −9
Original line number Original line Diff line number Diff line
@@ -607,15 +607,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
	if (test)
	if (test)
	    return;
	    return;


	/* Update regulatory */
	i = rate6mb;
	if (IS_CHAN_HT40(chan))
		i = rateHt40_0;
	else if (IS_CHAN_HT20(chan))
		i = rateHt20_0;

	regulatory->max_power_level = ratesArray[i];

	if (AR_SREV_9280_20_OR_LATER(ah)) {
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		for (i = 0; i < Ar5416RateSize; i++)
		for (i = 0; i < Ar5416RateSize; i++)
			ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
			ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
+0 −7
Original line number Original line Diff line number Diff line
@@ -746,13 +746,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
	if (test)
	if (test)
		return;
		return;


	if (IS_CHAN_2GHZ(chan))
		i = rate1l;
	else
		i = rate6mb;

	regulatory->max_power_level = ratesArray[i];

	if (AR_SREV_9280_20_OR_LATER(ah)) {
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		for (i = 0; i < Ar5416RateSize; i++)
		for (i = 0; i < Ar5416RateSize; i++)
			ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
			ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
+0 −11
Original line number Original line Diff line number Diff line
@@ -1167,17 +1167,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
			regulatory->max_power_level = ratesArray[i];
			regulatory->max_power_level = ratesArray[i];
	}
	}


	if (!test) {
		i = rate6mb;

		if (IS_CHAN_HT40(chan))
			i = rateHt40_0;
		else if (IS_CHAN_HT20(chan))
			i = rateHt20_0;

		regulatory->max_power_level = ratesArray[i];
	}

	switch(ar5416_get_ntxchains(ah->txchainmask)) {
	switch(ar5416_get_ntxchains(ah->txchainmask)) {
	case 1:
	case 1:
		break;
		break;