Commit 07053105 authored May 01, 2019 by Oscar A Perez Committed by Greg Kroah-Hartman Jan 27, 2020

ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit



[ Upstream commit 89b97c429e2e77d695b5133572ca12ec256a4ea4 ]

According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO
pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently
setting the upper limit to 220 which isn't allowing access to all their
GPIOs. The correct upper limit value is 232 (actual number is 228 plus a
4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work
correctly on a AST2500 BMC running Linux Kernel v4.19

Fixes: 2039f90d ("ARM: dts: aspeed-g5: Add gpio controller to devicetree")
Signed-off-by: Oscar A Perez <linux@neuralgames.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 68baab14

arch/arm/boot/dts/aspeed-g5.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -247,7 +247,7 @@
		compatible = "aspeed,ast2500-gpio";
		reg = <0x1e780000 0x1000>;
		interrupts = <20>;
		gpio-ranges = <&pinctrl 0 0 220>;
		gpio-ranges = <&pinctrl 0 0 232>;
		clocks = <&syscon ASPEED_CLK_APB>;
		interrupt-controller;
		};