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Commit 06edb80f authored by Andreas Färber's avatar Andreas Färber
Browse files

arm64: dts: Add Actions Semi S900 and Bubblegum-96 



Add Device Trees for Actions Semiconductor S900 SoC and
uCRobotics Bubblegum-96 board.

UART0/1/4/6 interrupts are guesses.

Cc: 96boards@ucrobotics.com
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 1c750fc1

arch/arm64/boot/dts/Makefile

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dts-dirs += actions

dts-dirs += al

dts-dirs += allwinner

dts-dirs += altera

arch/arm64/boot/dts/actions/Makefile

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dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb



always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb

arch/arm64/boot/dts/actions/s900-bubblegum-96.dts

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/*

 * Copyright (c) 2017 Andreas Färber

 *

 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)

 */



/dts-v1/;



#include "s900.dtsi"



/ {

	compatible = "ucrobotics,bubblegum-96", "actions,s900";

	model = "Bubblegum-96";



	aliases {

		serial5 = &uart5;

	};



	chosen {

		stdout-path = "serial5:115200n8";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0 0x0 0x80000000>;

	};

};



&timer {

	clocks = <&hosc>;

};



&uart5 {

	status = "okay";

};

arch/arm64/boot/dts/actions/s900.dtsi

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Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 Andreas Färber

 *

 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "actions,s900";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

		};

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		secmon@1f000000 {

			reg = <0x0 0x1f000000 0x0 0x1000000>;

			no-map;

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	arm-pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	hosc: hosc {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		#clock-cells = <0>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		gic: interrupt-controller@e00f1000 {

			compatible = "arm,gic-400";

			reg = <0x0 0xe00f1000 0x0 0x1000>,

			      <0x0 0xe00f2000 0x0 0x2000>,

			      <0x0 0xe00f4000 0x0 0x2000>,

			      <0x0 0xe00f6000 0x0 0x2000>;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

			interrupt-controller;

			#interrupt-cells = <3>;

		};



		uart0: serial@e0120000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe0120000 0x0 0x2000>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart1: serial@e0122000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe0122000 0x0 0x2000>;

			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart2: serial@e0124000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe0124000 0x0 0x2000>;

			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart3: serial@e0126000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe0126000 0x0 0x2000>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart4: serial@e0128000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe0128000 0x0 0x2000>;

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart5: serial@e012a000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe012a000 0x0 0x2000>;

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		uart6: serial@e012c000 {

			compatible = "actions,s900-uart", "actions,owl-uart";

			reg = <0x0 0xe012c000 0x0 0x2000>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		timer: timer@e0228000 {

			compatible = "actions,s900-timer";

			reg = <0x0 0xe0228000 0x0 0x8000>;

			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "timer1";

		};

	};

};