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Commit 06cd9a7d authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar
Browse files

x86: add x2apic config 



Impact: cleanup

so could deselect x2apic
and INTR_REMAP will select x2apic

Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 9f361c22

arch/x86/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -235,6 +235,20 @@ config SMP 


	  If you don't know what to do here, say N.



config X86_X2APIC

	bool "Support x2apic"

	depends on X86_LOCAL_APIC && X86_64

	---help---

	  This enables x2apic support on CPUs that have this feature.



	  This allows 32-bit apic IDs (so it can support very large systems),

	  and accesses the local apic via MSRs not via mmio.



	  ( On certain CPU models you may need to enable INTR_REMAP too,

	    to get functional x2apic mode. )



	  If you don't know what to do here, say N.



config SPARSE_IRQ

	bool "Support sparse irq numbering"

	depends on PCI_MSI || HT_IRQ
@@ -1828,6 +1842,7 @@ config DMAR_FLOPPY_WA 
config INTR_REMAP

	bool "Support for Interrupt Remapping (EXPERIMENTAL)"

	depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI && EXPERIMENTAL

	select X86_X2APIC

	---help---

	  Supports Interrupt remapping for IO-APIC and MSI devices.

	  To use x2apic mode in the CPU's which support x2APIC enhancements or

arch/x86/include/asm/apic.h

+15 −3
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ static inline u32 native_apic_msr_read(u32 reg) 
	return low;

}



#ifndef CONFIG_X86_32

#ifdef CONFIG_X86_X2APIC

extern int x2apic;

extern void check_x2apic(void);

extern void enable_x2apic(void);
@@ -131,7 +131,19 @@ static inline int x2apic_enabled(void) 
	return 0;

}

#else

#define x2apic_enabled()	0

static inline void check_x2apic(void)

{

}

static inline void enable_x2apic(void)

{

}

static inline void enable_IR_x2apic(void)

{

}

static inline int x2apic_enabled(void)

{

	return 0;

}

#endif



struct apic_ops {
@@ -177,7 +189,7 @@ static inline u32 safe_apic_wait_icr_idle(void) 


extern int get_physical_broadcast(void);



#ifdef CONFIG_X86_64

#ifdef CONFIG_X86_X2APIC

static inline void ack_x2APIC_irq(void)

{

	/* Docs say use 0 for future compatibility */

arch/x86/kernel/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -117,8 +117,8 @@ obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o # NB rename without _64 
# 64 bit specific files

ifeq ($(CONFIG_X86_64),y)

        obj-y				+= genapic_64.o genapic_flat_64.o

        obj-y				+= genx2apic_cluster.o

        obj-y				+= genx2apic_phys.o

        obj-$(CONFIG_X86_X2APIC)	+= genx2apic_cluster.o

        obj-$(CONFIG_X86_X2APIC)	+= genx2apic_phys.o

	obj-$(CONFIG_X86_UV)		+= genx2apic_uv_x.o tlb_uv.o

	obj-$(CONFIG_X86_UV)		+= bios_uv.o uv_irq.o uv_sysfs.o

        obj-$(CONFIG_X86_PM_TIMER)	+= pmtimer_64.o

arch/x86/kernel/apic.c

+12 −12
Original line number Diff line number Diff line
@@ -112,11 +112,7 @@ static __init int setup_apicpmtimer(char *s) 
__setup("apicpmtimer", setup_apicpmtimer);

#endif



#ifdef CONFIG_X86_64

#define HAVE_X2APIC

#endif



#ifdef HAVE_X2APIC

#ifdef CONFIG_X86_X2APIC

int x2apic;

/* x2apic enabled before OS handover */

static int x2apic_preenabled;
@@ -269,7 +265,7 @@ static struct apic_ops xapic_ops = { 
struct apic_ops __read_mostly *apic_ops = &xapic_ops;

EXPORT_SYMBOL_GPL(apic_ops);



#ifdef HAVE_X2APIC

#ifdef CONFIG_X86_X2APIC

static void x2apic_wait_icr_idle(void)

{

	/* no need to wait for icr idle in x2apic */
@@ -1320,11 +1316,14 @@ void __cpuinit end_local_APIC_setup(void) 
	apic_pm_activate();

}



#ifdef HAVE_X2APIC

#ifdef CONFIG_X86_X2APIC

void check_x2apic(void)

{

	int msr, msr2;



	if (!cpu_has_x2apic)

		return;



	rdmsr(MSR_IA32_APICBASE, msr, msr2);



	if (msr & X2APIC_ENABLE) {
@@ -1338,6 +1337,9 @@ void enable_x2apic(void) 
{

	int msr, msr2;



	if (!x2apic)

		return;



	rdmsr(MSR_IA32_APICBASE, msr, msr2);

	if (!(msr & X2APIC_ENABLE)) {

		pr_info("Enabling x2apic\n");
@@ -1439,7 +1441,7 @@ void __init enable_IR_x2apic(void) 


	return;

}

#endif /* HAVE_X2APIC */

#endif /* CONFIG_X86_X2APIC */



#ifdef CONFIG_X86_64

/*
@@ -1570,7 +1572,7 @@ void __init early_init_lapic_mapping(void) 
 */

void __init init_apic_mappings(void)

{

#ifdef HAVE_X2APIC

#ifdef CONFIG_X86_X2APIC

	if (x2apic) {

		boot_cpu_physical_apicid = read_apic_id();

		return;
@@ -1634,9 +1636,7 @@ int __init APIC_init_uniprocessor(void) 
	}

#endif



#ifdef HAVE_X2APIC

	enable_IR_x2apic();

#endif

#ifdef CONFIG_X86_64

	default_setup_apic_routing();

#endif
@@ -2021,7 +2021,7 @@ static int lapic_resume(struct sys_device *dev) 


	local_irq_save(flags);



#ifdef HAVE_X2APIC

#ifdef CONFIG_X86_X2APIC

	if (x2apic)

		enable_x2apic();

	else

arch/x86/kernel/cpu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -1051,7 +1051,7 @@ void __cpuinit cpu_init(void) 
	barrier();



	check_efer();

	if (cpu != 0 && x2apic)

	if (cpu != 0)

		enable_x2apic();



	/*