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Commit 06b35d93 authored by Piotr Luc's avatar Piotr Luc Committed by Thomas Gleixner
Browse files

x86/cpufeature: Add AVX512_VPOPCNTDQ feature 



Vector population count instructions for dwords and qwords are going to be
available in future Intel Xeon & Xeon Phi processors. Bit 14 of
CPUID[level:0x07, ECX] indicates that the instructions are supported by a
processor.

The specification can be found in the Intel Software Developer Manual (SDM)
and in the Instruction Set Extensions Programming Reference (ISE).

Populate the feature bit and clear it when xsave is disabled.

Signed-off-by: default avatarPiotr Luc <piotr.luc@intel.com>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
Cc: Radim Krčmář <rkrcmar@redhat.com>
Link: http://lkml.kernel.org/r/20170110173403.6010-2-piotr.luc@intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 49def185

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -288,6 +288,7 @@ 
#define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

#define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */

#define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */

#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */



/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
@@ -320,5 +321,4 @@ 
#define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */

#define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */

#define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */



#endif /* _ASM_X86_CPUFEATURES_H */

arch/x86/kernel/fpu/xstate.c

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ void fpu__xstate_clear_all_cpu_caps(void) 
	setup_clear_cpu_cap(X86_FEATURE_PKU);

	setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);

	setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);

	setup_clear_cpu_cap(X86_FEATURE_AVX512_VPOPCNTDQ);

}



/*

tools/arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -280,6 +280,7 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */

#define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */

#define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */

#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */



/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */

#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */