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Commit 06b23a9c authored by Krishna Kurapati's avatar Krishna Kurapati Committed by Krishna Kurapati PSSNV
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usb: dwc3-msm-core: Set pipectl susphy in conndone interrupt 



As per DesignWare Cores SuperSpeed USB 3.0 Controller Databook
Version 3.00a May 2015, section 8.1.3: Initialization on Connect
Done (Step-4)

GUSB2CFG/ GUSB3PIPECTL:
Depending on the connected speed, write to the other PHY’s control
register to suspend it

For SMMU Fault issue where the controller was accessing 0th address,
as per tests conducted, during core initialization, if the
GUSB3PIPECTL SUSPHY bit is set, the register writes (including GEVT)
are not going through and causing a CSR Timeout. As per databook, the
USB3 SUSPHY bit must be enabled after the link up happens in high
speed and not during core initialization. Fix this by clearing the
bit before core soft reset and setting it in conndone exit kretprobe
if the link up happens in high speed.

Change-Id: I6d416545220f65064a17248f1b1ba5a3a0a7eac2
Signed-off-by: default avatarKrishna Kurapati <quic_kriskura@quicinc.com>
parent 41e5131a

drivers/usb/dwc3/dwc3-msm.c

+28 −0
Original line number Diff line number Diff line
@@ -2005,6 +2005,24 @@ static void dwc3_gsi_event_buf_alloc(struct dwc3 *dwc) 
	}

}



static void dwc3_msm_modify_pipectl(struct dwc3 *dwc, bool set)

{

	struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);

	u32 reg;



	reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB3PIPECTL(0));



	if (set) {

		if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&

			(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))

			reg |= DWC3_GUSB3PIPECTL_SUSPHY;

	} else {

		reg &= ~(DWC3_GUSB3PIPECTL_SUSPHY);

	}



	dwc3_msm_write_reg(mdwc->base, DWC3_GUSB3PIPECTL(0), reg);

}



static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,

							unsigned int value)

{
@@ -2070,6 +2088,9 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, 
		break;

	case DWC3_CONTROLLER_CONNDONE_EVENT:

		dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n");



		dwc3_msm_modify_pipectl(dwc, true);



		/*

		 * Add power event if the dbm indicates coming out of L1 by

		 * interrupt
@@ -2194,6 +2215,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, 
		break;

	case DWC3_CONTROLLER_NOTIFY_CLEAR_DB:

		dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n");



		/*

		 * Clear the susphy bit here to ensure it is not set during

		 * the course of controller initialisation process.

		 */

		dwc3_msm_modify_pipectl(dwc, false);



		if (!mdwc->gsi_ev_buff)

			break;