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Commit 069e0c3c authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86/intel: Support full width counting 



Recent Intel CPUs like Haswell and IvyBridge have a new
alternative MSR range for perfctrs that allows writing the full
counter width. Enable this range if the hardware reports it
using a new capability bit.

Currently the perf code queries CPUID to get the counter width,
and sign extends the counter values as needed. The traditional
PERFCTR MSRs always limit to 32bit, even though the counter
internally is larger (usually 48 bits on recent CPUs)

When the new capability is set use the alternative range which
do not have these restrictions.

This lowers the overhead of perf stat slightly because it has to
do less interrupts to accumulate the counter value. On Haswell
it also avoids some problems with TSX aborting when the end of
the counter range is reached.

( See the patch "perf/x86/intel: Avoid checkpointed counters
  causing excessive TSX aborts" for more details. )

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Reviewed-by: default avatarStephane Eranian <eranian@google.com>
Acked-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1372173153-20215-1-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0c4df02d

arch/x86/include/uapi/asm/msr-index.h

+3 −0
Original line number Diff line number Diff line
@@ -170,6 +170,9 @@ 
#define MSR_KNC_EVNTSEL0               0x00000028

#define MSR_KNC_EVNTSEL1               0x00000029



/* Alternative perfctr range with full access. */

#define MSR_IA32_PMC0			0x000004c1



/* AMD64 MSRs. Not complete. See the architecture manual for a more

   complete list. */

arch/x86/kernel/cpu/perf_event.h

+5 −0
Original line number Diff line number Diff line
@@ -310,6 +310,11 @@ union perf_capabilities { 
		u64	pebs_arch_reg:1;

		u64	pebs_format:4;

		u64	smm_freeze:1;

		/*

		 * PMU supports separate counter range for writing

		 * values > 32bit.

		 */

		u64	full_width_write:1;

	};

	u64	capabilities;

};

arch/x86/kernel/cpu/perf_event_intel.c

+7 −0
Original line number Diff line number Diff line
@@ -2340,5 +2340,12 @@ __init int intel_pmu_init(void) 
		}

	}



	/* Support full width counters using alternative MSR range */

	if (x86_pmu.intel_cap.full_width_write) {

		x86_pmu.max_period = x86_pmu.cntval_mask;

		x86_pmu.perfctr = MSR_IA32_PMC0;

		pr_cont("full-width counters, ");

	}



	return 0;

}