Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0689aad7 authored by Xia Yang's avatar Xia Yang Committed by Ben Skeggs
Browse files

drm/nouveau/fifo/gk104: fix chid bit mask 



Fix the channel id bit mask in FIFO schedule timeout error handling.

FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID      is bit 11:0  thus 0x00000fff.

Signed-off-by: default avatarXia Yang <xiay@nvidia.com>
Reviewed-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 9d0394c6

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

+2 −2
Original line number Diff line number Diff line
@@ -198,11 +198,11 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) 
	for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {

		u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));

		u32 busy = (stat & 0x80000000);

		u32 next = (stat & 0x07ff0000) >> 16;

		u32 next = (stat & 0x0fff0000) >> 16;

		u32 chsw = (stat & 0x00008000);

		u32 save = (stat & 0x00004000);

		u32 load = (stat & 0x00002000);

		u32 prev = (stat & 0x000007ff);

		u32 prev = (stat & 0x00000fff);

		u32 chid = load ? next : prev;

		(void)save;