Merge "drm/msm: set sde rsc min threshold time" (068368da) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/msm/sde_rsc.c

+10 −9

Original line number	Diff line number	Diff line
		@@ -421,7 +421,7 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc,
		/* mode 2 is infinite */
		rsc->timer_config.rsc_time_slot_2_ns = 0xFFFFFFFF;

		rsc->timer_config.min_threshold_time_ns = MIN_THRESHOLD_TIME;
		rsc->timer_config.min_threshold_time_ns = 0;
		rsc->timer_config.bwi_threshold_time_ns =
		rsc->timer_config.rsc_time_slot_0_ns;

		@@ -1458,18 +1458,19 @@ static int sde_rsc_probe(struct platform_device *pdev)
		else
		rsc->single_tcs_execution_time = SINGLE_TCS_EXECUTION_TIME_V1;

		rsc->backoff_time_ns = rsc->single_tcs_execution_time
		+ RSC_MODE_INSTRUCTION_TIME;

		rsc->mode_threshold_time_ns = rsc->backoff_time_ns
		+ RSC_MODE_THRESHOLD_OVERHEAD;

		if (rsc->version == SDE_RSC_REV_3)
		if (rsc->version == SDE_RSC_REV_3) {
		rsc->time_slot_0_ns = rsc->single_tcs_execution_time
		+ RSC_MODE_INSTRUCTION_TIME;
		else
		rsc->backoff_time_ns = RSC_MODE_INSTRUCTION_TIME;
		rsc->mode_threshold_time_ns = rsc->time_slot_0_ns;
		} else {
		rsc->time_slot_0_ns = (rsc->single_tcs_execution_time * 2)
		+ RSC_MODE_INSTRUCTION_TIME;
		rsc->backoff_time_ns = rsc->single_tcs_execution_time
		+ RSC_MODE_INSTRUCTION_TIME;
		rsc->mode_threshold_time_ns = rsc->backoff_time_ns
		+ RSC_MODE_THRESHOLD_OVERHEAD;
		}

		ret = sde_power_resource_init(pdev, &rsc->phandle);
		if (ret) {

drivers/gpu/drm/msm/sde_rsc_hw.c

+2 −2

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "[sde_rsc_hw:%s:%d]: " fmt, __func__, __LINE__
		@@ -293,7 +293,7 @@ static int rsc_hw_solver_init(struct sde_rsc_priv *rsc)
		return 0;
		}

		int rsc_hw_timer_update(struct sde_rsc_priv *rsc)
		static int rsc_hw_timer_update(struct sde_rsc_priv *rsc)
		{
		if (!rsc) {
		pr_debug("invalid input param\n");

drivers/gpu/drm/msm/sde_rsc_hw.h

+1 −3

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/*
		* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef _SDE_RSC_HW_H_
		@@ -102,8 +102,6 @@ int rsc_hw_vsync(struct sde_rsc_priv *rsc, enum rsc_vsync_req request,

		bool rsc_hw_is_amc_mode(struct sde_rsc_priv *rsc);

		int rsc_hw_timer_update(struct sde_rsc_priv *rsc);

		void rsc_hw_debug_dump(struct sde_rsc_priv *rsc, u32 mux_sel);

		int sde_rsc_debug_show(struct seq_file s, struct sde_rsc_priv rsc);

drivers/gpu/drm/msm/sde_rsc_hw_v3.c

+46 −2

Original line number	Diff line number	Diff line
		@@ -205,7 +205,8 @@ static int _rsc_hw_solver_init(struct sde_rsc_priv *rsc)
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE1,
		0x80000000, rsc->debug_mode);
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE1,
		rsc->timer_config.rsc_backoff_time_ns, rsc->debug_mode);
		rsc->timer_config.rsc_backoff_time_ns * 2,
		rsc->debug_mode);
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE1,
		rsc->timer_config.pdc_backoff_time_ns, rsc->debug_mode);

		@@ -542,6 +543,49 @@ int rsc_hw_bwi_status_v3(struct sde_rsc_priv *rsc, bool bw_indication)
		return rc;
		}

		static int rsc_hw_timer_update_v3(struct sde_rsc_priv *rsc)
		{
		if (!rsc) {
		pr_debug("invalid input param\n");
		return -EINVAL;
		}

		pr_debug("rsc hw timer update\n");

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_1_DRV0,
		rsc->timer_config.rsc_time_slot_0_ns, rsc->debug_mode);
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_2_DRV0,
		rsc->timer_config.rsc_time_slot_1_ns, rsc->debug_mode);
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_3_DRV0,
		rsc->timer_config.rsc_time_slot_2_ns, rsc->debug_mode);

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE0,
		rsc->timer_config.rsc_backoff_time_ns, rsc->debug_mode);
		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE0,
		rsc->timer_config.pdc_backoff_time_ns, rsc->debug_mode);

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE1,
		rsc->timer_config.rsc_backoff_time_ns * 2,
		rsc->debug_mode);

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE1,
		rsc->timer_config.pdc_backoff_time_ns, rsc->debug_mode);

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE2,
		rsc->timer_config.pdc_backoff_time_ns, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_STATIC_WAKEUP_0,
		rsc->timer_config.static_wakeup_time_ns, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_RSCC_MODE_THRESHOLD,
		rsc->timer_config.rsc_mode_threshold_time_ns, rsc->debug_mode);

		/* make sure that hw timers are updated */
		wmb();

		return 0;
		}

		int sde_rsc_hw_register_v3(struct sde_rsc_priv *rsc)
		{
		pr_debug("rsc hardware register v3\n");
		@@ -549,10 +593,10 @@ int sde_rsc_hw_register_v3(struct sde_rsc_priv *rsc)
		rsc->hw_ops.init = rsc_hw_init_v3;
		rsc->hw_ops.state_update = sde_rsc_state_update_v3;
		rsc->hw_ops.bwi_status = rsc_hw_bwi_status_v3;
		rsc->hw_ops.timer_update = rsc_hw_timer_update_v3;

		rsc->hw_ops.tcs_wait = rsc_hw_tcs_wait;
		rsc->hw_ops.tcs_use_ok = rsc_hw_tcs_use_ok;
		rsc->hw_ops.timer_update = rsc_hw_timer_update;
		rsc->hw_ops.is_amc_mode = rsc_hw_is_amc_mode;
		rsc->hw_ops.hw_vsync = rsc_hw_vsync;
		rsc->hw_ops.debug_show = sde_rsc_debug_show;