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Commit 06456f41 authored by Swetha Chikkaboraiah's avatar Swetha Chikkaboraiah Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update CPU nodes 

Update CPU nodes for SDM49 as per the driver.

Change-Id: I3e4f7019f6a9bcc3cd9e4e1722a4a7aaf67ee6d7
parent 297e6b44

qcom/sdm429-cpu.dtsi

+4 −14
Original line number Diff line number Diff line
@@ -31,25 +31,21 @@ 
			reg = <0x100>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x90000000>;

			efficiency = <1024>;

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      /* A53 L2 dump not supported */

			      qcom,dump-size = <0x0>;

			};



			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -59,18 +55,16 @@ 
			reg = <0x101>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x90000000>;

			efficiency = <1024>;

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -80,18 +74,16 @@ 
			reg = <0x102>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x90000000>;

			efficiency = <1024>;

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};
@@ -101,18 +93,16 @@ 
			reg = <0x103>;

			enable-method = "psci";

			cpu-release-addr = <0x0 0x90000000>;

			efficiency = <1024>;

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};

		};