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Commit 0608d4db authored by Tariq Toukan's avatar Tariq Toukan Committed by Saeed Mahameed
Browse files

net/mlx5e: Unify slow PCI heuristic 



Get the link/pci speed query and logic into a single function.
Unify the heuristics and use a single PCI threshold (16G) for all.

Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 5d22d47b

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+14 −17
Original line number Diff line number Diff line
@@ -3902,16 +3902,20 @@ static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) 
	return 0;

}



static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)

static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)

{

	return (link_speed && pci_bw &&

		(pci_bw < 40000) && (pci_bw < link_speed));

}

	u32 link_speed = 0;

	u32 pci_bw = 0;



static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)

{

	return !(link_speed && pci_bw &&

		 (pci_bw <= 16000) && (pci_bw < link_speed));

	mlx5e_get_max_linkspeed(mdev, &link_speed);

	mlx5e_get_pci_bw(mdev, &pci_bw);

	mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",

			   link_speed, pci_bw);



#define MLX5E_SLOW_PCI_RATIO (2)



	return link_speed && pci_bw &&

		link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;

}



void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
@@ -3980,17 +3984,10 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, 
			    u16 max_channels)

{

	u8 cq_period_mode = 0;

	u32 link_speed = 0;

	u32 pci_bw = 0;



	params->num_channels = max_channels;

	params->num_tc       = 1;



	mlx5e_get_max_linkspeed(mdev, &link_speed);

	mlx5e_get_pci_bw(mdev, &pci_bw);

	mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",

		      link_speed, pci_bw);



	/* SQ */

	params->log_sq_size = is_kdump_kernel() ?

		MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
@@ -4000,7 +3997,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, 
	params->rx_cqe_compress_def = false;

	if (MLX5_CAP_GEN(mdev, cqe_compression) &&

	    MLX5_CAP_GEN(mdev, vport_group_manager))

		params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);

		params->rx_cqe_compress_def = slow_pci_heuristic(mdev);



	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
@@ -4011,7 +4008,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, 


	/* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */

	if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)

		params->lro_en = hw_lro_heuristic(link_speed, pci_bw);

		params->lro_en = !slow_pci_heuristic(mdev);

	params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);



	/* CQ moderation params */

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

+5 −0
Original line number Diff line number Diff line
@@ -50,6 +50,11 @@ extern uint mlx5_core_debug_mask; 
		 __func__, __LINE__, current->pid,			\

		 ##__VA_ARGS__)



#define mlx5_core_dbg_once(__dev, format, ...)				\

	dev_dbg_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,	\

		     __func__, __LINE__, current->pid,			\

		     ##__VA_ARGS__)



#define mlx5_core_dbg_mask(__dev, mask, format, ...)			\

do {									\

	if ((mask) & mlx5_core_debug_mask)				\