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Commit 06067a2f authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

ARM: dts: sun7i: rename clock node names to clk@N 



Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 7b5b2909

arch/arm/boot/dts/sun7i-a20.dtsi

+17 −8
Original line number Diff line number Diff line
@@ -54,11 +54,12 @@ 
		#size-cells = <1>;

		ranges;



		osc24M: osc24M@01c20050 {

		osc24M: clk@01c20050 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-osc-clk";

			reg = <0x01c20050 0x4>;

			clock-frequency = <24000000>;

			clock-output-names = "osc24M";

		};



		osc32k: clk@0 {
@@ -68,21 +69,23 @@ 
			clock-output-names = "osc32k";

		};



		pll1: pll1@01c20000 {

		pll1: clk@01c20000 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			reg = <0x01c20000 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll1";

		};



		pll4: pll4@01c20018 {

		pll4: clk@01c20018 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			reg = <0x01c20018 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll4";

		};



		pll5: pll5@01c20020 {

		pll5: clk@01c20020 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-pll5-clk";

			reg = <0x01c20020 0x4>;
@@ -90,7 +93,7 @@ 
			clock-output-names = "pll5_ddr", "pll5_other";

		};



		pll6: pll6@01c20028 {

		pll6: clk@01c20028 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-pll6-clk";

			reg = <0x01c20028 0x4>;
@@ -103,6 +106,7 @@ 
			compatible = "allwinner,sun4i-cpu-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;

			clock-output-names = "cpu";

		};



		axi: axi@01c20054 {
@@ -110,6 +114,7 @@ 
			compatible = "allwinner,sun4i-axi-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&cpu>;

			clock-output-names = "axi";

		};



		ahb: ahb@01c20054 {
@@ -117,9 +122,10 @@ 
			compatible = "allwinner,sun4i-ahb-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&axi>;

			clock-output-names = "ahb";

		};



		ahb_gates: ahb_gates@01c20060 {

		ahb_gates: clk@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun7i-a20-ahb-gates-clk";

			reg = <0x01c20060 0x8>;
@@ -144,9 +150,10 @@ 
			compatible = "allwinner,sun4i-apb0-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&ahb>;

			clock-output-names = "apb0";

		};



		apb0_gates: apb0_gates@01c20068 {

		apb0_gates: clk@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun7i-a20-apb0-gates-clk";

			reg = <0x01c20068 0x4>;
@@ -162,6 +169,7 @@ 
			compatible = "allwinner,sun4i-apb1-mux-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;

			clock-output-names = "apb1_mux";

		};



		apb1: apb1@01c20058 {
@@ -169,9 +177,10 @@ 
			compatible = "allwinner,sun4i-apb1-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&apb1_mux>;

			clock-output-names = "apb1";

		};



		apb1_gates: apb1_gates@01c2006c {

		apb1_gates: clk@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun7i-a20-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;