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Commit 05d1e255 authored by raghavendra ambadas's avatar raghavendra ambadas Committed by Nirmal Abraham
Browse files

clk: qcom: mdss: Add check to read the gdsc status 



Add check for 28NM pll interface to read the
gdsc status bit for QM215 target.

Change-Id: I3167950ce4ec16e553e15330f5deb6de4a3619c4
Signed-off-by: default avatarRaghavendra Ambadas <rambad@codeaurora.org>
Signed-off-by: default avatarNirmal Abraham <nabrah@codeaurora.org>
parent d64fa8eb

drivers/clk/qcom/mdss/mdss-pll.h

+3 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. */



#ifndef __MDSS_PLL_H

#define __MDSS_PLL_H
@@ -218,7 +218,8 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) 
		WARN(1, "gdsc_base register is not defined\n");

		return true;

	}

	if (pll_res->target_id == MDSS_PLL_TARGET_SDM660)

	if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) ||

			(pll_res->pll_interface_type == MDSS_DSI_PLL_28LPM))

		ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&

		(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true;

	else