Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 04ebcb54 authored by Emilio López's avatar Emilio López Committed by Maxime Ripard
Browse files

ARM: sun7i: fix PLL4 clock and add PLL8 



Allwinner reworked the PLL4 clock in sun7i; so we need to change the
compatible. Additionally, PLL8 is compatible with this new PLL4
implementation, so let's add a node for it as well.

Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent c9eaa447

arch/arm/boot/dts/sun7i-a20.dtsi

+9 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ 


		pll4: clk@01c20018 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-pll1-clk";

			compatible = "allwinner,sun7i-a20-pll4-clk";

			reg = <0x01c20018 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll4";
@@ -109,6 +109,14 @@ 
			clock-output-names = "pll6_sata", "pll6_other", "pll6";

		};



		pll8: clk@01c20040 {

			#clock-cells = <0>;

			compatible = "allwinner,sun7i-a20-pll4-clk";

			reg = <0x01c20040 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll8";

		};



		cpu: cpu@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-cpu-clk";