Merge branch 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux into drm-next

	  Choose this option if you want to enable experimental support

	  for SI asics.

	  SI is already supported in radeon. Experimental support for SI

	  in amdgpu will be disabled by default and is still provided by

	  radeon. Use module options to override this:

	  radeon.si_support=0 amdgpu.si_support=1

config DRM_AMDGPU_CIK

	bool "Enable amdgpu support for CIK parts"

	depends on DRM_AMDGPU

	help

	  Choose this option if you want to enable experimental support

	  for CIK asics.

	  Choose this option if you want to enable support for CIK asics.

	  CIK is already supported in radeon. Support for CIK in amdgpu

	  will be disabled by default and is still provided by radeon.

	  Use module options to override this:

	  CIK is already supported in radeon.  CIK support in amdgpu

	  is for experimentation and testing.

	  radeon.cik_support=0 amdgpu.cik_support=1

config DRM_AMDGPU_USERPTR

	bool "Always enable userptr write support"

	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_queue_mgr.o

# add asic specific block

amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o

amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o

# add GMC block

amdgpu-y += \

# add PSP block

amdgpu-y += \

	amdgpu_psp.o \

	psp_v3_1.o

	psp_v3_1.o \

	psp_v10_0.o

# add SMC block

amdgpu-y += \

	vce_v3_0.o \

	vce_v4_0.o

# add VCN block

amdgpu-y += \

	amdgpu_vcn.o \

	vcn_v1_0.o

# add amdkfd interfaces

amdgpu-y += \

	 amdgpu_amdkfd.o \

#include <drm/drm_gem.h>

#include <drm/amdgpu_drm.h>

#include <kgd_kfd_interface.h>

#include "amd_shared.h"

#include "amdgpu_mode.h"

#include "amdgpu_ih.h"

#include "amdgpu_acp.h"

#include "amdgpu_uvd.h"

#include "amdgpu_vce.h"

#include "amdgpu_vcn.h"

#include "gpu_scheduler.h"

#include "amdgpu_virt.h"

extern int amdgpu_vm_block_size;

extern int amdgpu_vm_fault_stop;

extern int amdgpu_vm_debug;

extern int amdgpu_vm_update_mode;

extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_no_evict;

extern int amdgpu_pos_buf_per_se;

extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_param_buf_per_se;

extern int amdgpu_job_hang_limit;

extern int amdgpu_lbpw;

#ifdef CONFIG_DRM_AMDGPU_SI

extern int amdgpu_si_support;

#endif

#ifdef CONFIG_DRM_AMDGPU_CIK

extern int amdgpu_cik_support;

#endif

#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

	/* set pte flags based per asic */

	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,

				     uint32_t flags);

	/* adjust mc addr in fb for APU case */

	u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);

	/* get the pde for a given mc addr */

	u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);

	uint32_t (*get_invalidate_req)(unsigned int vm_id);

};

void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);

int amdgpu_gart_init(struct amdgpu_device *adev);

void amdgpu_gart_fini(struct amdgpu_device *adev);

void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,

int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,

			int pages);

int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,

		     int pages, struct page **pagelist,

	uint32_t                srbm_soft_reset;

	struct amdgpu_mode_mc_save save;

	bool			prt_warning;

	uint64_t		stolen_size;

	/* apertures */

	u64					shared_aperture_start;

	u64					shared_aperture_end;

		      struct amd_sched_entity *entity, void *owner,

		      struct dma_fence **f);

/*

 * Queue manager

 */

struct amdgpu_queue_mapper {

	int 		hw_ip;

	struct mutex	lock;

	/* protected by lock */

	struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];

};

struct amdgpu_queue_mgr {

	struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];

};

int amdgpu_queue_mgr_init(struct amdgpu_device *adev,

			  struct amdgpu_queue_mgr *mgr);

int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,

			  struct amdgpu_queue_mgr *mgr);

int amdgpu_queue_mgr_map(struct amdgpu_device *adev,

			 struct amdgpu_queue_mgr *mgr,

			 int hw_ip, int instance, int ring,

			 struct amdgpu_ring **out_ring);

/*

 * context related structures

 */

struct amdgpu_ctx {

	struct kref		refcount;

	struct amdgpu_device    *adev;

	struct amdgpu_queue_mgr queue_mgr;

	unsigned		reset_counter;

	spinlock_t		ring_lock;

	struct dma_fence	**fences;

	struct mutex		bo_list_lock;

	struct idr		bo_list_handles;

	struct amdgpu_ctx_mgr	ctx_mgr;

	u32			vram_lost_counter;

};

/*

	u32 *register_restore;

};

#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES

struct amdgpu_mec {

	struct amdgpu_bo	*hpd_eop_obj;

	u64			hpd_eop_gpu_addr;

	struct amdgpu_bo	*mec_fw_obj;

	u64			mec_fw_gpu_addr;

	u32 num_pipe;

	u32 num_mec;

	u32 num_queue;

	u32 num_pipe_per_mec;

	u32 num_queue_per_pipe;

	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];

	/* These are the resources for which amdgpu takes ownership */

	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

};

struct amdgpu_kiq {

	u64			eop_gpu_addr;

	struct amdgpu_bo	*eop_obj;

	struct mutex		ring_mutex;

	struct amdgpu_ring	ring;

	struct amdgpu_irq_src	irq;

};

struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t max_waves_per_simd;

	uint32_t wave_front_size;

	uint32_t max_scratch_slots_per_cu;

	uint32_t lds_size;

	uint32_t bitmap[4][4];

};

	uint32_t                        grbm_soft_reset;

	uint32_t                        srbm_soft_reset;

	bool                            in_reset;

	/* s3/s4 mask */

	bool                            in_suspend;

	/* NGG */

	struct amdgpu_ngg		ngg;

};

#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */

#define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in virtual memory context */

struct amdgpu_job {

	struct amd_sched_job    base;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_sync	dep_sync;

	struct amdgpu_sync	sched_sync;

	struct amdgpu_ib	*ibs;

	struct dma_fence	*fence; /* the hw fence */

	uint32_t		preamble_status;

	void			*owner;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	bool			need_pipeline_sync;

	unsigned		vm_id;

	uint64_t		vm_pd_addr;

	uint32_t		gds_base, gds_size;

	const struct amdgpu_psp_funcs *funcs;

	struct amdgpu_bo *rbuf;

	struct mutex mutex;

	/* gpu info firmware data pointer */

	const struct firmware *gpu_info_fw;

};

/*

 */

struct amdgpu_allowed_register_entry {

	uint32_t reg_offset;

	bool untouched;

	bool grbm_indexed;

};

typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);

#define AMDGPU_RESET_MAGIC_NUM 64

struct amdgpu_device {

	struct device			*dev;

	struct drm_device		*ddev;

	atomic64_t			gtt_usage;

	atomic64_t			num_bytes_moved;

	atomic64_t			num_evictions;

	atomic64_t			num_vram_cpu_page_faults;

	atomic_t			gpu_reset_counter;

	atomic_t			vram_lost_counter;

	/* data for buffer migration throttling */

	struct {

	/* sdma */

	struct amdgpu_sdma		sdma;

	union {

		struct {

			/* uvd */

			struct amdgpu_uvd		uvd;

			/* vce */

			struct amdgpu_vce		vce;

		};

		/* vcn */

		struct amdgpu_vcn		vcn;

	};

	/* firmwares */

	struct amdgpu_firmware		firmware;

	/* amdkfd interface */

	struct kfd_dev          *kfd;

	/* delayed work_func for deferring clockgating during resume */

	struct delayed_work     late_init_work;

	struct amdgpu_virt	virt;

	/* link all shadow bo */

	/* link all gtt */

	spinlock_t			gtt_list_lock;

	struct list_head                gtt_list;

	/* keep an lru list of rings by HW IP */

	struct list_head		ring_lru_list;

	spinlock_t			ring_lru_list_lock;

	/* record hw reset is performed */

	bool has_hw_reset;

	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];

};

	return container_of(bdev, struct amdgpu_device, mman.bdev);

}

bool amdgpu_device_is_px(struct drm_device *dev);

int amdgpu_device_init(struct amdgpu_device *adev,

		       struct drm_device *ddev,

		       struct pci_dev *pdev,

	unsigned occupied, chunk1, chunk2;

	void *dst;

	if (ring->count_dw < count_dw) {

	if (unlikely(ring->count_dw < count_dw)) {

		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	} else {

		return;

	}

	occupied = ring->wptr & ring->buf_mask;

	dst = (void *)&ring->ring[occupied];

	chunk1 = ring->buf_mask + 1 - occupied;

	ring->wptr &= ring->ptr_mask;

	ring->count_dw -= count_dw;

}

}

static inline struct amdgpu_sdma_instance *

amdgpu_get_sdma_instance(struct amdgpu_ring *ring)

#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))

#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))

#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))

#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))

#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

void amdgpu_update_display_priority(struct amdgpu_device *adev);

int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);

int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,

		       u32 ip_instance, u32 ring,

		       struct amdgpu_ring **out_ring);

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);

void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);

extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];

extern const int amdgpu_max_kms_ioctl;

bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,

			  struct amdgpu_fpriv *fpriv);

int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);

void amdgpu_driver_unload_kms(struct drm_device *dev);

void amdgpu_driver_lastclose_kms(struct drm_device *dev);

#include "amd_shared.h"

#include <drm/drmP.h>

#include "amdgpu.h"

#include "amdgpu_gfx.h"

#include <linux/module.h>

const struct kfd2kgd_calls *kfd2kgd;

	return ret;

}

bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev)

bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev)

{

	switch (rdev->asic_type) {

	switch (adev->asic_type) {

#ifdef CONFIG_DRM_AMDGPU_CIK

	case CHIP_KAVERI:

		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();

	}

}

void amdgpu_amdkfd_device_probe(struct amdgpu_device *rdev)

void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)

{

	if (kgd2kfd)

		rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev,

					rdev->pdev, kfd2kgd);

		adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,

					adev->pdev, kfd2kgd);

}

void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev)

void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)

{

	if (rdev->kfd) {

	int i;

	int last_valid_bit;

	if (adev->kfd) {

		struct kgd2kfd_shared_resources gpu_resources = {

			.compute_vmid_bitmap = 0xFF00,

			.first_compute_pipe = 1,

			.compute_pipe_count = 4 - 1,

			.num_mec = adev->gfx.mec.num_mec,

			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,

			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe

		};

		amdgpu_doorbell_get_kfd_info(rdev,

		/* this is going to have a few of the MSBs set that we need to

		 * clear */

		bitmap_complement(gpu_resources.queue_bitmap,

				  adev->gfx.mec.queue_bitmap,

				  KGD_MAX_QUEUES);

		/* remove the KIQ bit as well */

		if (adev->gfx.kiq.ring.ready)

			clear_bit(amdgpu_gfx_queue_to_bit(adev,

							  adev->gfx.kiq.ring.me - 1,

							  adev->gfx.kiq.ring.pipe,

							  adev->gfx.kiq.ring.queue),

				  gpu_resources.queue_bitmap);

		/* According to linux/bitmap.h we shouldn't use bitmap_clear if

		 * nbits is not compile time constant */

		last_valid_bit = adev->gfx.mec.num_mec

				* adev->gfx.mec.num_pipe_per_mec

				* adev->gfx.mec.num_queue_per_pipe;

		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)

			clear_bit(i, gpu_resources.queue_bitmap);

		amdgpu_doorbell_get_kfd_info(adev,

				&gpu_resources.doorbell_physical_address,

				&gpu_resources.doorbell_aperture_size,

				&gpu_resources.doorbell_start_offset);

		kgd2kfd->device_init(rdev->kfd, &gpu_resources);

		kgd2kfd->device_init(adev->kfd, &gpu_resources);

	}

}

void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev)

void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)

{

	if (rdev->kfd) {

		kgd2kfd->device_exit(rdev->kfd);

		rdev->kfd = NULL;

	if (adev->kfd) {

		kgd2kfd->device_exit(adev->kfd);

		adev->kfd = NULL;

	}

}

void amdgpu_amdkfd_interrupt(struct amdgpu_device *rdev,

void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,

		const void *ih_ring_entry)

{

	if (rdev->kfd)

		kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);

	if (adev->kfd)

		kgd2kfd->interrupt(adev->kfd, ih_ring_entry);

}

void amdgpu_amdkfd_suspend(struct amdgpu_device *rdev)

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)

{

	if (rdev->kfd)

		kgd2kfd->suspend(rdev->kfd);

	if (adev->kfd)

		kgd2kfd->suspend(adev->kfd);

}

int amdgpu_amdkfd_resume(struct amdgpu_device *rdev)

int amdgpu_amdkfd_resume(struct amdgpu_device *adev)

{

	int r = 0;

	if (rdev->kfd)

		r = kgd2kfd->resume(rdev->kfd);

	if (adev->kfd)

		r = kgd2kfd->resume(adev->kfd);

	return r;

}

			void **mem_obj, uint64_t *gpu_addr,

			void **cpu_ptr)

{

	struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	struct kgd_mem **mem = (struct kgd_mem **) mem_obj;

	int r;

	if ((*mem) == NULL)

		return -ENOMEM;

	r = amdgpu_bo_create(rdev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,

	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,

			     AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, &(*mem)->bo);

	if (r) {

		dev_err(rdev->dev,

		dev_err(adev->dev,

			"failed to allocate BO for amdkfd (%d)\n", r);

		return r;

	}

	/* map the buffer */

	r = amdgpu_bo_reserve((*mem)->bo, true);

	if (r) {

		dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);

		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);

		goto allocate_mem_reserve_bo_failed;

	}

	r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT,

				&(*mem)->gpu_addr);

	if (r) {

		dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);

		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);

		goto allocate_mem_pin_bo_failed;

	}

	*gpu_addr = (*mem)->gpu_addr;

	r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);

	if (r) {

		dev_err(rdev->dev,

		dev_err(adev->dev,

			"(%d) failed to map bo to kernel for amdkfd\n", r);

		goto allocate_mem_kmap_bo_failed;

	}

uint64_t get_vmem_size(struct kgd_dev *kgd)

{

	struct amdgpu_device *rdev =

	struct amdgpu_device *adev =

		(struct amdgpu_device *)kgd;

	BUG_ON(kgd == NULL);

	return rdev->mc.real_vram_size;

	return adev->mc.real_vram_size;

}

uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)

{

	struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (rdev->gfx.funcs->get_gpu_clock_counter)

		return rdev->gfx.funcs->get_gpu_clock_counter(rdev);

	if (adev->gfx.funcs->get_gpu_clock_counter)

		return adev->gfx.funcs->get_gpu_clock_counter(adev);

	return 0;

}

uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)

{

	struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	/* The sclk is in quantas of 10kHz */

	return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;

	return adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;

}

int amdgpu_amdkfd_init(void);

void amdgpu_amdkfd_fini(void);

bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev);

bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev);

void amdgpu_amdkfd_suspend(struct amdgpu_device *rdev);

int amdgpu_amdkfd_resume(struct amdgpu_device *rdev);

void amdgpu_amdkfd_interrupt(struct amdgpu_device *rdev,

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev);

int amdgpu_amdkfd_resume(struct amdgpu_device *adev);

void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,

			const void *ih_ring_entry);

void amdgpu_amdkfd_device_probe(struct amdgpu_device *rdev);

void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev);

void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev);

void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);

void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);

void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);