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Commit 047486d8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:

 - Altera: L2 cache and On-Chip RAM support (Thor Thayer).

 - EDAC: Workqueue handling cleanups (Borislav Petkov).

 - Xgene: Register bus error handling (Loc Ho).

 - Misc small fixes.

* tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  ARM: socfpga: Enable OCRAM ECC on startup
  ARM: socfpga: Enable L2 cache ECC on startup
  ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries
  EDAC, altera: Add Altera L2 cache and OCRAM support
  EDAC: Use edac_debugfs_remove_recursive() in edac_debugfs_exit()
  EDAC, mpc85xx: Silence unused variable warning
  EDAC: Cleanup/sync workqueue functions
  EDAC: Kill workqueue setup/teardown functions
  EDAC: Balance workqueue setup and teardown
  arm64: Update the APM X-Gene EDAC node with the RB register resource
  EDAC, xgene: Add missing SoC register bus error handling
  Documentation, EDAC: Update xgene binding for missing register bus
  EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
parents 9256d5a3 7cc5a5d3

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

0 → 100644
+49 −0
Original line number Diff line number Diff line 
Altera SoCFPGA ECC Manager

This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.

The ECC Manager counts and corrects single bit errors and counts/handles

double bit errors which are uncorrectable.



Required Properties:

- compatible : Should be "altr,socfpga-ecc-manager"

- #address-cells: must be 1

- #size-cells: must be 1

- ranges : standard definition, should translate from local addresses



Subcomponents:



L2 Cache ECC

Required Properties:

- compatible : Should be "altr,socfpga-l2-ecc"

- reg : Address and size for ECC error interrupt clear registers.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.



On Chip RAM ECC

Required Properties:

- compatible : Should be "altr,socfpga-ocram-ecc"

- reg : Address and size for ECC error interrupt clear registers.

- iram : phandle to On-Chip RAM definition.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.



Example:



	eccmgr: eccmgr@ffd08140 {

		compatible = "altr,socfpga-ecc-manager";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		l2-ecc@ffd08140 {

			compatible = "altr,socfpga-l2-ecc";

			reg = <0xffd08140 0x4>;

			interrupts = <0 36 1>, <0 37 1>;

		};



		ocram-ecc@ffd08144 {

			compatible = "altr,socfpga-ocram-ecc";

			reg = <0xffd08144 0x4>;

			iram = <&ocram>;

			interrupts = <0 178 1>, <0 179 1>;

		};

	};

Documentation/devicetree/bindings/edac/apm-xgene-edac.txt

+10 −0
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ Required properties: 
- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.

- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.

- regmap-efuse		: Regmap of the PMD efuse resource.

- regmap-rb		: Regmap of the register bus resource. This property

			  is optional only for compatibility. If the RB

			  error conditions are not cleared, it will

			  continuously generate interrupt.

- reg			: First resource shall be the CPU bus (PCP) resource.

- interrupts            : Interrupt-specifier for MCU, PMD, L3, or SoC error

			  IRQ(s).
@@ -64,6 +68,11 @@ Example: 
		reg = <0x0 0x1054a000 0x0 0x20>;

	};



	rb: rb@7e000000 {

		compatible = "apm,xgene-rb", "syscon";

		reg = <0x0 0x7e000000 0x0 0x10>;

	};



	edac@78800000 {

		compatible = "apm,xgene-edac";

		#address-cells = <2>;
@@ -73,6 +82,7 @@ Example: 
		regmap-mcba = <&mcba>;

		regmap-mcbb = <&mcbb>;

		regmap-efuse = <&efuse>;

		regmap-rb = <&rb>;

		reg = <0x0 0x78800000 0x0 0x100>;

		interrupts = <0x0 0x20 0x4>,

			     <0x0 0x21 0x4>,

arch/arm/boot/dts/socfpga.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -656,6 +656,26 @@ 
			status = "disabled";

		};



		eccmgr: eccmgr@ffd08140 {

			compatible = "altr,socfpga-ecc-manager";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			l2-ecc@ffd08140 {

				compatible = "altr,socfpga-l2-ecc";

				reg = <0xffd08140 0x4>;

				interrupts = <0 36 1>, <0 37 1>;

			};



			ocram-ecc@ffd08144 {

				compatible = "altr,socfpga-ocram-ecc";

				reg = <0xffd08144 0x4>;

				iram = <&ocram>;

				interrupts = <0 178 1>, <0 179 1>;

			};

		};



		L2: l2-cache@fffef000 {

			compatible = "arm,pl310-cache";

			reg = <0xfffef000 0x1000>;

arch/arm/mach-socfpga/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -5,3 +5,5 @@ 
obj-y					:= socfpga.o

obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o

obj-$(CONFIG_SOCFPGA_SUSPEND)	+= pm.o self-refresh.o

obj-$(CONFIG_EDAC_ALTERA_L2C)	+= l2_cache.o

obj-$(CONFIG_EDAC_ALTERA_OCRAM)	+= ocram.o

arch/arm/mach-socfpga/core.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 


extern void socfpga_init_clocks(void);

extern void socfpga_sysmgr_init(void);

void socfpga_init_l2_ecc(void);

void socfpga_init_ocram_ecc(void);



extern void __iomem *sys_manager_base_addr;

extern void __iomem *rst_manager_base_addr;