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Commit 03d85f86 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "dt-bindings: clock: gcc-bengal: Remove the throttle clocks"

parents 924d3589 0f560fc0

drivers/clk/qcom/gcc-bengal.c

+0 −46
Original line number Diff line number Diff line
@@ -2546,34 +2546,6 @@ static struct clk_branch gcc_cpuss_gnoc_clk = { 
	},

};



static struct clk_branch gcc_cpuss_throttle_core_clk = {

	.halt_reg = 0x2b180,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b180,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(30),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_cpuss_throttle_xo_clk = {

	.halt_reg = 0x2b17c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2b17c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_xo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_disp_ahb_clk = {

	.halt_reg = 0x1700c,

	.halt_check = BRANCH_HALT,
@@ -2928,21 +2900,6 @@ static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 
	},

};



static struct clk_branch gcc_qmip_cpuss_cfg_ahb_clk = {

	.halt_reg = 0x2b178,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b178,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(18),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qmip_cpuss_cfg_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qmip_disp_ahb_clk = {

	.halt_reg = 0x17018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -3711,8 +3668,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { 
	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,

	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,

	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,

	[GCC_CPUSS_THROTTLE_CORE_CLK] = &gcc_cpuss_throttle_core_clk.clkr,

	[GCC_CPUSS_THROTTLE_XO_CLK] = &gcc_cpuss_throttle_xo_clk.clkr,

	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,

	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,

	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
@@ -3740,7 +3695,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { 
	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,

	[GCC_QMIP_CPUSS_CFG_AHB_CLK] = &gcc_qmip_cpuss_cfg_ahb_clk.clkr,

	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,

	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,

	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,

include/dt-bindings/clock/qcom,gcc-bengal.h

+106 −109
Original line number Diff line number Diff line
@@ -66,115 +66,112 @@ 
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				56

#define GCC_CPUSS_AHB_CLK					57

#define GCC_CPUSS_GNOC_CLK					60

#define GCC_CPUSS_THROTTLE_CORE_CLK				61

#define GCC_CPUSS_THROTTLE_XO_CLK				62

#define GCC_DISP_AHB_CLK					63

#define GCC_DISP_GPLL0_DIV_CLK_SRC				64

#define GCC_DISP_HF_AXI_CLK					65

#define GCC_DISP_THROTTLE_CORE_CLK				66

#define GCC_DISP_XO_CLK						67

#define GCC_GP1_CLK						68

#define GCC_GP1_CLK_SRC						69

#define GCC_GP2_CLK						70

#define GCC_GP2_CLK_SRC						71

#define GCC_GP3_CLK						72

#define GCC_GP3_CLK_SRC						73

#define GCC_GPU_CFG_AHB_CLK					74

#define GCC_GPU_GPLL0_CLK_SRC					75

#define GCC_GPU_GPLL0_DIV_CLK_SRC				76

#define GCC_GPU_IREF_CLK					77

#define GCC_GPU_MEMNOC_GFX_CLK					78

#define GCC_GPU_SNOC_DVM_GFX_CLK				79

#define GCC_GPU_THROTTLE_CORE_CLK				80

#define GCC_GPU_THROTTLE_XO_CLK					81

#define GCC_PDM2_CLK						82

#define GCC_PDM2_CLK_SRC					83

#define GCC_PDM_AHB_CLK						84

#define GCC_PDM_XO4_CLK						85

#define GCC_PRNG_AHB_CLK					86

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				87

#define GCC_QMIP_CAMERA_RT_AHB_CLK				88

#define GCC_QMIP_CPUSS_CFG_AHB_CLK				89

#define GCC_QMIP_DISP_AHB_CLK					90

#define GCC_QMIP_GPU_CFG_AHB_CLK				91

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				92

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				93

#define GCC_QUPV3_WRAP0_CORE_CLK				94

#define GCC_QUPV3_WRAP0_S0_CLK					95

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				96

#define GCC_QUPV3_WRAP0_S1_CLK					97

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				98

#define GCC_QUPV3_WRAP0_S2_CLK					99

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				100

#define GCC_QUPV3_WRAP0_S3_CLK					101

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				102

#define GCC_QUPV3_WRAP0_S4_CLK					103

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				104

#define GCC_QUPV3_WRAP0_S5_CLK					105

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				106

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				107

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				108

#define GCC_SDCC1_AHB_CLK					109

#define GCC_SDCC1_APPS_CLK					110

#define GCC_SDCC1_APPS_CLK_SRC					111

#define GCC_SDCC1_ICE_CORE_CLK					112

#define GCC_SDCC1_ICE_CORE_CLK_SRC				113

#define GCC_SDCC2_AHB_CLK					114

#define GCC_SDCC2_APPS_CLK					115

#define GCC_SDCC2_APPS_CLK_SRC					116

#define GCC_SYS_NOC_CPUSS_AHB_CLK				117

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK				118

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK				119

#define GCC_UFS_PHY_AHB_CLK					120

#define GCC_UFS_PHY_AXI_CLK					121

#define GCC_UFS_PHY_AXI_CLK_SRC					122

#define GCC_UFS_PHY_ICE_CORE_CLK				123

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				124

#define GCC_UFS_PHY_PHY_AUX_CLK					125

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				126

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				127

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				128

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				129

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				130

#define GCC_USB30_PRIM_MASTER_CLK				131

#define GCC_USB30_PRIM_MASTER_CLK_SRC				132

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				133

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			134

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		135

#define GCC_USB30_PRIM_SLEEP_CLK				136

#define GCC_USB3_PRIM_CLKREF_CLK				137

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				138

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				139

#define GCC_USB3_PRIM_PHY_PIPE_CLK				140

#define GCC_VCODEC0_AXI_CLK					141

#define GCC_VENUS_AHB_CLK					142

#define GCC_VENUS_CTL_AXI_CLK					143

#define GCC_VIDEO_AHB_CLK					144

#define GCC_VIDEO_AXI0_CLK					145

#define GCC_VIDEO_THROTTLE_CORE_CLK				146

#define GCC_VIDEO_VCODEC0_SYS_CLK				147

#define GCC_VIDEO_VENUS_CLK_SRC					148

#define GCC_VIDEO_VENUS_CTL_CLK					149

#define GCC_VIDEO_XO_CLK					150

#define GCC_AHB2PHY_CSI_CLK					151

#define GCC_AHB2PHY_USB_CLK					152

#define GCC_BIMC_GPU_AXI_CLK					153

#define GCC_BOOT_ROM_AHB_CLK					154

#define GCC_CAM_THROTTLE_NRT_CLK				155

#define GCC_CAM_THROTTLE_RT_CLK					156

#define GCC_CAMERA_AHB_CLK					157

#define GCC_CAMERA_XO_CLK					158

#define GCC_CAMSS_AXI_CLK					159

#define GCC_CAMSS_AXI_CLK_SRC					160

#define GCC_CAMSS_CAMNOC_ATB_CLK				161

#define GCC_CAMSS_CAMNOC_NTS_XO_CLK				162

#define GCC_CAMSS_CCI_0_CLK					163

#define GCC_CAMSS_CCI_CLK_SRC					164

#define GCC_CAMSS_CPHY_0_CLK					165

#define GCC_CAMSS_CPHY_1_CLK					166

#define GCC_CAMSS_CPHY_2_CLK					167

#define GCC_UFS_CLKREF_CLK					168

#define GCC_DISP_GPLL0_CLK_SRC					169

#define GCC_DISP_AHB_CLK					61

#define GCC_DISP_GPLL0_DIV_CLK_SRC				62

#define GCC_DISP_HF_AXI_CLK					63

#define GCC_DISP_THROTTLE_CORE_CLK				64

#define GCC_DISP_XO_CLK						65

#define GCC_GP1_CLK						66

#define GCC_GP1_CLK_SRC						67

#define GCC_GP2_CLK						68

#define GCC_GP2_CLK_SRC						69

#define GCC_GP3_CLK						70

#define GCC_GP3_CLK_SRC						71

#define GCC_GPU_CFG_AHB_CLK					72

#define GCC_GPU_GPLL0_CLK_SRC					73

#define GCC_GPU_GPLL0_DIV_CLK_SRC				74

#define GCC_GPU_IREF_CLK					75

#define GCC_GPU_MEMNOC_GFX_CLK					76

#define GCC_GPU_SNOC_DVM_GFX_CLK				77

#define GCC_GPU_THROTTLE_CORE_CLK				78

#define GCC_GPU_THROTTLE_XO_CLK					79

#define GCC_PDM2_CLK						80

#define GCC_PDM2_CLK_SRC					81

#define GCC_PDM_AHB_CLK						82

#define GCC_PDM_XO4_CLK						83

#define GCC_PRNG_AHB_CLK					84

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				85

#define GCC_QMIP_CAMERA_RT_AHB_CLK				86

#define GCC_QMIP_DISP_AHB_CLK					87

#define GCC_QMIP_GPU_CFG_AHB_CLK				88

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				89

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				90

#define GCC_QUPV3_WRAP0_CORE_CLK				91

#define GCC_QUPV3_WRAP0_S0_CLK					92

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				93

#define GCC_QUPV3_WRAP0_S1_CLK					94

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				95

#define GCC_QUPV3_WRAP0_S2_CLK					96

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				97

#define GCC_QUPV3_WRAP0_S3_CLK					98

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				99

#define GCC_QUPV3_WRAP0_S4_CLK					100

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				101

#define GCC_QUPV3_WRAP0_S5_CLK					102

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				103

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				104

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				105

#define GCC_SDCC1_AHB_CLK					106

#define GCC_SDCC1_APPS_CLK					107

#define GCC_SDCC1_APPS_CLK_SRC					108

#define GCC_SDCC1_ICE_CORE_CLK					109

#define GCC_SDCC1_ICE_CORE_CLK_SRC				110

#define GCC_SDCC2_AHB_CLK					111

#define GCC_SDCC2_APPS_CLK					112

#define GCC_SDCC2_APPS_CLK_SRC					113

#define GCC_SYS_NOC_CPUSS_AHB_CLK				114

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK				115

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK				116

#define GCC_UFS_PHY_AHB_CLK					117

#define GCC_UFS_PHY_AXI_CLK					118

#define GCC_UFS_PHY_AXI_CLK_SRC					119

#define GCC_UFS_PHY_ICE_CORE_CLK				120

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				121

#define GCC_UFS_PHY_PHY_AUX_CLK					122

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				123

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				124

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				125

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				126

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				127

#define GCC_USB30_PRIM_MASTER_CLK				128

#define GCC_USB30_PRIM_MASTER_CLK_SRC				129

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				130

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			131

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		132

#define GCC_USB30_PRIM_SLEEP_CLK				133

#define GCC_USB3_PRIM_CLKREF_CLK				134

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				135

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				136

#define GCC_USB3_PRIM_PHY_PIPE_CLK				137

#define GCC_VCODEC0_AXI_CLK					138

#define GCC_VENUS_AHB_CLK					139

#define GCC_VENUS_CTL_AXI_CLK					140

#define GCC_VIDEO_AHB_CLK					141

#define GCC_VIDEO_AXI0_CLK					142

#define GCC_VIDEO_THROTTLE_CORE_CLK				143

#define GCC_VIDEO_VCODEC0_SYS_CLK				144

#define GCC_VIDEO_VENUS_CLK_SRC					145

#define GCC_VIDEO_VENUS_CTL_CLK					146

#define GCC_VIDEO_XO_CLK					147

#define GCC_AHB2PHY_CSI_CLK					148

#define GCC_AHB2PHY_USB_CLK					149

#define GCC_BIMC_GPU_AXI_CLK					150

#define GCC_BOOT_ROM_AHB_CLK					151

#define GCC_CAM_THROTTLE_NRT_CLK				152

#define GCC_CAM_THROTTLE_RT_CLK					153

#define GCC_CAMERA_AHB_CLK					154

#define GCC_CAMERA_XO_CLK					155

#define GCC_CAMSS_AXI_CLK					156

#define GCC_CAMSS_AXI_CLK_SRC					157

#define GCC_CAMSS_CAMNOC_ATB_CLK				158

#define GCC_CAMSS_CAMNOC_NTS_XO_CLK				159

#define GCC_CAMSS_CCI_0_CLK					160

#define GCC_CAMSS_CCI_CLK_SRC					161

#define GCC_CAMSS_CPHY_0_CLK					162

#define GCC_CAMSS_CPHY_1_CLK					163

#define GCC_CAMSS_CPHY_2_CLK					164

#define GCC_UFS_CLKREF_CLK					165

#define GCC_DISP_GPLL0_CLK_SRC					166



/* GCC resets */

#define GCC_QUSB2PHY_PRIM_BCR					0