Merge "Merge android-4.19-q.69 (93083852) into msm-4.19" (02fe6eea) · Commits · e / devices / android_kernel_oneplus_sm7250

Documentation/admin-guide/kernel-parameters.txt

+7 −0

Original line number	Diff line number	Diff line
		@@ -3959,6 +3959,13 @@
		Run specified binary instead of /init from the ramdisk,
		used for early userspace startup. See initrd.

		rdrand= [X86]
		force - Override the decision by the kernel to hide the
		advertisement of RDRAND support (this affects
		certain AMD processors because of buggy BIOS
		support, specifically around the suspend/resume
		path).

		rdt= [HW,X86,RDT]
		Turn on/off individual RDT features. List is:
		cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp,

Makefile

+1 −1

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: GPL-2.0
		VERSION = 4
		PATCHLEVEL = 19
		SUBLEVEL = 68
		SUBLEVEL = 69
		EXTRAVERSION =
		NAME = "People's Front"

arch/arm/kvm/coproc.c

+15 −8

Original line number	Diff line number	Diff line
		@@ -658,13 +658,22 @@ int kvm_handle_cp14_64(struct kvm_vcpu vcpu, struct kvm_run run)
		}

		static void reset_coproc_regs(struct kvm_vcpu *vcpu,
		const struct coproc_reg *table, size_t num)
		const struct coproc_reg *table, size_t num,
		unsigned long *bmap)
		{
		unsigned long i;

		for (i = 0; i < num; i++)
		if (table[i].reset)
		if (table[i].reset) {
		int reg = table[i].reg;

		table[i].reset(vcpu, &table[i]);
		if (reg > 0 && reg < NR_CP15_REGS) {
		set_bit(reg, bmap);
		if (table[i].is_64bit)
		set_bit(reg + 1, bmap);
		}
		}
		}

		static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu)
		@@ -1439,17 +1448,15 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
		{
		size_t num;
		const struct coproc_reg *table;

		/* Catch someone adding a register without putting in reset entry. */
		memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15));
		DECLARE_BITMAP(bmap, NR_CP15_REGS) = { 0, };

		/* Generic chip reset first (so target could override). */
		reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
		reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs), bmap);

		table = get_target_table(vcpu->arch.target, &num);
		reset_coproc_regs(vcpu, table, num);
		reset_coproc_regs(vcpu, table, num, bmap);

		for (num = 1; num < NR_CP15_REGS; num++)
		WARN(vcpu_cp15(vcpu, num) == 0x42424242,
		WARN(!test_bit(num, bmap),
		"Didn't reset vcpu_cp15(vcpu, %zi)", num);
		}

arch/arm64/kvm/sys_regs.c

+18 −14

Original line number	Diff line number	Diff line
		@@ -626,7 +626,7 @@ static void reset_pmcr(struct kvm_vcpu vcpu, const struct sys_reg_desc r)
		*/
		val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
		\| (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
		__vcpu_sys_reg(vcpu, PMCR_EL0) = val;
		__vcpu_sys_reg(vcpu, r->reg) = val;
		}

		static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
		@@ -968,13 +968,13 @@ static bool access_pmuserenr(struct kvm_vcpu vcpu, struct sys_reg_params p,
		/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
		#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
		{ SYS_DESC(SYS_DBGBVRn_EL1(n)), \
		trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
		trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
		{ SYS_DESC(SYS_DBGBCRn_EL1(n)), \
		trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
		trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
		{ SYS_DESC(SYS_DBGWVRn_EL1(n)), \
		trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
		trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
		{ SYS_DESC(SYS_DBGWCRn_EL1(n)), \
		trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
		trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }

		/* Macro to expand the PMEVCNTRn_EL0 register */
		#define PMU_PMEVCNTR_EL0(n) \
		@@ -1359,7 +1359,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {

		{ SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 },

		{ SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },
		{ SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
		{ SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
		{ SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
		{ SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
		@@ -2072,13 +2072,19 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu,
		}

		static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
		const struct sys_reg_desc *table, size_t num)
		const struct sys_reg_desc *table, size_t num,
		unsigned long *bmap)
		{
		unsigned long i;

		for (i = 0; i < num; i++)
		if (table[i].reset)
		if (table[i].reset) {
		int reg = table[i].reg;

		table[i].reset(vcpu, &table[i]);
		if (reg > 0 && reg < NR_SYS_REGS)
		set_bit(reg, bmap);
		}
		}

		/**
		@@ -2576,18 +2582,16 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
		{
		size_t num;
		const struct sys_reg_desc *table;

		/* Catch someone adding a register without putting in reset entry. */
		memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
		DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, };

		/* Generic chip reset first (so target could override). */
		reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
		reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap);

		table = get_target_table(vcpu->arch.target, true, &num);
		reset_sys_reg_descs(vcpu, table, num);
		reset_sys_reg_descs(vcpu, table, num, bmap);

		for (num = 1; num < NR_SYS_REGS; num++) {
		if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242,
		if (WARN(!test_bit(num, bmap),
		"Didn't reset __vcpu_sys_reg(%zi)\n", num))
		break;
		}

arch/mips/kernel/cacheinfo.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -80,6 +80,8 @@ static int __populate_cache_leaves(unsigned int cpu)
		if (c->tcache.waysize)
		populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);

		this_cpu_ci->cpu_map_populated = true;

		return 0;
		}