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Commit 022d1a29 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

Just some minor fixes for VM reg check and a regression fix for dce3 plls

* 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/si: add some missing regs to the VM reg checker
  drm/radeon/cayman: add some missing regs to the VM reg checker
  drm/radeon/dce3: switch back to old pll allocation order for discrete
parents 695ddeb4 f418b88a

drivers/gpu/drm/radeon/atombios_crtc.c

+31 −23
Original line number Diff line number Diff line
@@ -1696,8 +1696,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {

		if (ASIC_IS_AVIVO(rdev)) {

	} else if (ASIC_IS_AVIVO(rdev)) {

		/* in DP mode, the DP ref clock can come from either PPLL

		 * depending on the asic:

		 * DCE3: PPLL1 or PPLL2
@@ -1715,10 +1714,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		}

		/* all other cases */

		pll_in_use = radeon_get_pll_use_mask(crtc);

		/* the order shouldn't matter here, but we probably

		 * need this until we have atomic modeset

		 */

		if (rdev->flags & RADEON_IS_IGP) {

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

		} else {

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

		}

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {
@@ -1726,7 +1735,6 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		return radeon_crtc->crtc_id;

	}

}

}



void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)

{

drivers/gpu/drm/radeon/evergreen_cs.c

+3 −0
Original line number Diff line number Diff line
@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg) 
	/* check config regs */

	switch (reg) {

	case GRBM_GFX_INDEX:

	case CP_STRMOUT_CNTL:

	case CP_COHER_CNTL:

	case CP_COHER_SIZE:

	case VGT_VTX_VECT_EJECT_REG:

	case VGT_CACHE_INVALIDATION:

	case VGT_GS_VERTEX_REUSE:

drivers/gpu/drm/radeon/evergreend.h

+4 −0
Original line number Diff line number Diff line
@@ -91,6 +91,10 @@ 
#define		FB_READ_EN					(1 << 0)

#define		FB_WRITE_EN					(1 << 1)



#define	CP_STRMOUT_CNTL					0x84FC



#define	CP_COHER_CNTL					0x85F0

#define	CP_COHER_SIZE					0x85F4

#define	CP_COHER_BASE					0x85F8

#define	CP_STALLED_STAT1			0x8674

#define	CP_STALLED_STAT2			0x8678

drivers/gpu/drm/radeon/si.c

+1 −0
Original line number Diff line number Diff line
@@ -2474,6 +2474,7 @@ static bool si_vm_reg_valid(u32 reg) 
	/* check config regs */

	switch (reg) {

	case GRBM_GFX_INDEX:

	case CP_STRMOUT_CNTL:

	case VGT_VTX_VECT_EJECT_REG:

	case VGT_CACHE_INVALIDATION:

	case VGT_ESGS_RING_SIZE:

drivers/gpu/drm/radeon/sid.h

+1 −0
Original line number Diff line number Diff line
@@ -424,6 +424,7 @@ 
#       define RDERR_INT_ENABLE                         (1 << 0)

#       define GUI_IDLE_INT_ENABLE                      (1 << 19)



#define	CP_STRMOUT_CNTL					0x84FC

#define	SCRATCH_REG0					0x8500

#define	SCRATCH_REG1					0x8504

#define	SCRATCH_REG2					0x8508