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Commit 021eca99 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update GPU clock node for LITO"

parents 1894e057 d310251d

arch/arm64/boot/dts/qcom/lito-gdsc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -128,7 +128,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		domain-addr = <&gpu_gx_domain_addr>;

arch/arm64/boot/dts/qcom/lito.dtsi

+14 −8
Original line number Diff line number Diff line
@@ -912,7 +912,7 @@ 
	};



	dispcc: qcom,dispcc {

		compatible = "qcom,lito-dispcc";

		compatible = "qcom,lito-dispcc", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		clock-names = "cfg_ahb_clk";
@@ -922,6 +922,16 @@ 
		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc {

		compatible = "qcom,gpucc-lito", "syscon";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";
@@ -1055,13 +1065,6 @@ 
		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	apps_rsc: rsc@18200000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";
@@ -1536,10 +1539,13 @@ 
};



&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_GFX_LEVEL>;

	vdd_parent-supply = <&VDD_GFX_LEVEL>;

	status = "ok";

};