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Commit 020594a8 authored by Tingwei Zhang's avatar Tingwei Zhang Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add jtag mm node for Kona 



Add jtag mm device node for Kona to enable etm save and
restore function.

Change-Id: I3a1c7c4140bea3ecb7344da88a338e6352b13917
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 561fd240

arch/arm64/boot/dts/qcom/kona.dtsi

+88 −0
Original line number Diff line number Diff line
@@ -508,6 +508,94 @@ 
		};

	};



	jtag_mm0: jtagmm@7040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7040000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@7140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7140000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@7240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7240000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@7340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7340000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	jtag_mm4: jtagmm@7440000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7440000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU4>;

	};



	jtag_mm5: jtagmm@7540000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7540000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU5>;

	};



	jtag_mm6: jtagmm@7640000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7640000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU6>;

	};



	jtag_mm7: jtagmm@7740000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7740000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};



	qcom,devfreq-l3 {

		compatible = "qcom,devfreq-fw";

		reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>;