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Commit 01c0dad6 authored by Yujun Zhang's avatar Yujun Zhang
Browse files

disp: pll: add support for 10nm DSI PLL shadow clock 



Add support for 10nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.

Change-Id: Ib61bc5dcb5304bc1e3c7568c1419737580da3c88
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
Signed-off-by: default avatarYujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: default avatarRay Zhang <rayz@codeaurora.org>
parent 90ae2587

pll/dsi_pll_10nm.c

+592 −28

File changed.

Preview size limit exceeded, changes collapsed.

pll/dsi_pll_14nm_util.c

+3 −3
Original line number Diff line number Diff line
@@ -34,12 +34,12 @@ static int mdss_pll_read_stored_trim_codes( 
		goto end_read;

	}



	for (i = 0; i < dsi_pll_res->dfps->panel_dfps.frame_rate_cnt; i++) {

	for (i = 0; i < dsi_pll_res->dfps->vco_rate_cnt; i++) {

		struct dfps_codes_info *codes_info =

			&dsi_pll_res->dfps->codes_dfps[i];



		pr_debug("valid=%d frame_rate=%d, vco_rate=%d, code %d %d\n",

			codes_info->is_valid, codes_info->frame_rate,

		pr_debug("valid=%d frame_rate=%d, code %d %d\n",

			codes_info->is_valid,

			codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,

			codes_info->pll_codes.pll_codes_2);

pll/pll_drv.h

+11 −11
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
		writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \

			(base) + (offset))



#define upper_8_bit(x) ((((x) >> 2) & 0x100) >> 8)



enum {

	MDSS_DSI_PLL_10NM,

	MDSS_DP_PLL_10NM,
@@ -51,30 +53,23 @@ enum { 
	MDSS_PLL_TARGET_8996,

};



#define DFPS_MAX_NUM_OF_FRAME_RATES 20



struct dfps_panel_info {

	uint32_t enabled;

	uint32_t frame_rate_cnt;

	uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */

};

#define DFPS_MAX_NUM_OF_FRAME_RATES 16



struct dfps_pll_codes {

	uint32_t pll_codes_1;

	uint32_t pll_codes_2;

	uint32_t pll_codes_3;

};



struct dfps_codes_info {

	uint32_t is_valid;

	uint32_t frame_rate;	/* hz */

	uint32_t clk_rate;	/* hz */

	struct dfps_pll_codes pll_codes;

};



struct dfps_info {

	struct dfps_panel_info panel_dfps;

	uint32_t vco_rate_cnt;

	struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];

	void *dfps_fb_base;

};



struct mdss_pll_resources {
@@ -149,7 +144,7 @@ struct mdss_pll_resources { 
	/*

	 * caching the pll trim codes in the case of dynamic refresh

	 */

	int		cache_pll_trim_codes[2];

	int		cache_pll_trim_codes[3];



	/*

	 * for maintaining the status of saving trim codes
@@ -191,6 +186,11 @@ struct mdss_pll_resources { 
	 */

	struct dfps_info *dfps;



	/*

	 * for cases where dfps trigger happens before first

	 * suspend/resume and handoff is not finished.

	 */

	bool dfps_trigger;

};



struct mdss_pll_vco_calc {