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Commit 0182dcc5 authored by Mark Brown's avatar Mark Brown
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ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs



When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 1ca04065
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+1 −3
Original line number Diff line number Diff line
@@ -519,7 +519,7 @@ static int configure_clock(struct snd_soc_codec *codec)
		dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);

		reg = wm8993_read(codec, WM8993_CLOCKING_2);
		reg &= ~WM8993_SYSCLK_SRC;
		reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
		if (wm8993->mclk_rate > 13500000) {
			reg |= WM8993_MCLK_DIV;
			wm8993->sysclk_rate = wm8993->mclk_rate / 2;
@@ -527,8 +527,6 @@ static int configure_clock(struct snd_soc_codec *codec)
			reg &= ~WM8993_MCLK_DIV;
			wm8993->sysclk_rate = wm8993->mclk_rate;
		}
		reg &= ~WM8993_MCLK_DIV;
		reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
		wm8993_write(codec, WM8993_CLOCKING_2, reg);
		break;