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Commit 01687781 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next 

A few more things for 4.12:
- ttm and amdgpu support for non-contiguous vram CPU mappings
- lots of bug fixes and cleanups for vega10
- misc bug fixes and code cleanups

[airlied: fix do_div error on 32-bit arm, not sure it's 100% correct]

* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (58 commits)
  drm/amdgpu: use uintptr_t instead of unsigned long to store pointer
  drm/amdgpu: Avoid using signed integer to store pointer value
  drm/amdgpu:invoke new implemented AI MB func
  drm/amdgpu/vega10:timeout set to equal with VI
  drm/amdgpu:implement the reset MB func for vega10
  drm/amdgpu:fix typo for mxgpu_ai
  drm/amdgpu:no need to involv HDP in KIQ
  drm/amdgpu:add PSP block only load_type=PSP (v2)
  drm/amdgpu/smu9: update to latest driver interface
  drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()
  drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset()
  drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()
  drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable()
  drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()
  drm/amd/amdgpu: Drop gfx_v9_0_print_status()
  drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state()
  drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state()
  drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()
  drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()
  drm/amdgpu: Move function amdgpu_has_atpx near other similar functions
  ...
parents aed93ee7 f4e7c7c1

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+14 −17
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include <linux/wait.h>

#include <linux/list.h>

#include <linux/kref.h>

#include <linux/interval_tree.h>

#include <linux/rbtree.h>

#include <linux/hashtable.h>

#include <linux/dma-fence.h>
@@ -122,14 +122,6 @@ extern int amdgpu_param_buf_per_se; 
/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		2



/* max number of VMHUB */

#define AMDGPU_MAX_VMHUBS			2

#define AMDGPU_MMHUB				0

#define AMDGPU_GFXHUB				1



/* hardcode that limit for now */

#define AMDGPU_VA_RESERVED_SIZE			(8 << 20)



/* hard reset data */

#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
@@ -312,12 +304,9 @@ struct amdgpu_gart_funcs { 
	/* set pte flags based per asic */

	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,

				     uint32_t flags);

};



/* provided by the mc block */

struct amdgpu_mc_funcs {

	/* adjust mc addr in fb for APU case */

	u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);

	uint32_t (*get_invalidate_req)(unsigned int vm_id);

};



/* provided by the ih block */
@@ -379,7 +368,10 @@ struct amdgpu_bo_list_entry { 


struct amdgpu_bo_va_mapping {

	struct list_head		list;

	struct interval_tree_node	it;

	struct rb_node			rb;

	uint64_t			start;

	uint64_t			last;

	uint64_t			__subtree_last;

	uint64_t			offset;

	uint64_t			flags;

};
@@ -579,8 +571,6 @@ struct amdgpu_vmhub { 
	uint32_t	vm_context0_cntl;

	uint32_t	vm_l2_pro_fault_status;

	uint32_t	vm_l2_pro_fault_cntl;

	uint32_t	(*get_invalidate_req)(unsigned int vm_id);

	uint32_t	(*get_vm_protection_bits)(void);

};



/*
@@ -618,7 +608,6 @@ struct amdgpu_mc { 
	u64					private_aperture_end;

	/* protects concurrent invalidation */

	spinlock_t		invalidate_lock;

	const struct amdgpu_mc_funcs *mc_funcs;

};



/*
@@ -1712,6 +1701,12 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 
#define WREG32_FIELD(reg, field, val)	\

	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\

	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



#define WREG32_FIELD15(ip, idx, reg, field, val)	\

	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



/*

 * BIOS helpers.

 */
@@ -1887,12 +1882,14 @@ void amdgpu_unregister_atpx_handler(void); 
bool amdgpu_has_atpx_dgpu_power_cntl(void);

bool amdgpu_is_atpx_hybrid(void);

bool amdgpu_atpx_dgpu_req_power_for_displays(void);

bool amdgpu_has_atpx(void);

#else

static inline void amdgpu_register_atpx_handler(void) {}

static inline void amdgpu_unregister_atpx_handler(void) {}

static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }

static inline bool amdgpu_is_atpx_hybrid(void) { return false; }

static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }

static inline bool amdgpu_has_atpx(void) { return false; }

#endif



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

+29 −0
Original line number Diff line number Diff line
@@ -754,6 +754,35 @@ union igp_info { 
	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;

};



/*

 * Return vram width from integrated system info table, if available,

 * or 0 if not.

 */

int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);

	u16 data_offset, size;

	union igp_info *igp_info;

	u8 frev, crev;



	/* get any igp specific overrides */

	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,

				   &frev, &crev, &data_offset)) {

		igp_info = (union igp_info *)

			(mode_info->atom_context->bios + data_offset);

		switch (crev) {

		case 8:

		case 9:

			return igp_info->info_8.ucUMAChannelNumber * 64;

		default:

			return 0;

		}

	}



	return 0;

}



static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,

						 struct amdgpu_atom_ss *ss,

						 int id)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

+2 −0
Original line number Diff line number Diff line
@@ -148,6 +148,8 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev); 


int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev);



int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev);



bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,

				      struct amdgpu_atom_ss *ss,

				      int id, u32 clock);

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

+1 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	union drm_amdgpu_bo_list *args = data;

	uint32_t handle = args->in.list_handle;

	const void __user *uptr = (const void*)(long)args->in.bo_info_ptr;

	const void __user *uptr = (const void*)(uintptr_t)args->in.bo_info_ptr;



	struct drm_amdgpu_bo_list_entry *info;

	struct amdgpu_bo_list *list;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+10 −10
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
	}



	/* get chunks */

	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);

	chunk_array_user = (uint64_t __user *)(uintptr_t)(cs->in.chunks);

	if (copy_from_user(chunk_array, chunk_array_user,

			   sizeof(uint64_t)*cs->in.num_chunks)) {

		ret = -EFAULT;
@@ -181,7 +181,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
		struct drm_amdgpu_cs_chunk user_chunk;

		uint32_t __user *cdata;



		chunk_ptr = (void __user *)(unsigned long)chunk_array[i];

		chunk_ptr = (void __user *)(uintptr_t)chunk_array[i];

		if (copy_from_user(&user_chunk, chunk_ptr,

				       sizeof(struct drm_amdgpu_cs_chunk))) {

			ret = -EFAULT;
@@ -192,7 +192,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
		p->chunks[i].length_dw = user_chunk.length_dw;



		size = p->chunks[i].length_dw;

		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (void __user *)(uintptr_t)user_chunk.chunk_data;



		p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));

		if (p->chunks[i].kdata == NULL) {
@@ -949,7 +949,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 
			}



			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >

			    (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {

			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {

				DRM_ERROR("IB va_start+ib_bytes is invalid\n");

				return -EINVAL;

			}
@@ -960,7 +960,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 
				return r;

			}



			offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;

			offset = m->start * AMDGPU_GPU_PAGE_SIZE;

			kptr += chunk_ib->va_start - offset;



			r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
@@ -1339,7 +1339,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 
	if (fences == NULL)

		return -ENOMEM;



	fences_user = (void __user *)(unsigned long)(wait->in.fences);

	fences_user = (void __user *)(uintptr_t)(wait->in.fences);

	if (copy_from_user(fences, fences_user,

		sizeof(struct drm_amdgpu_fence) * fence_count)) {

		r = -EFAULT;
@@ -1388,8 +1388,8 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
			continue;



		list_for_each_entry(mapping, &lobj->bo_va->valids, list) {

			if (mapping->it.start > addr ||

			    addr > mapping->it.last)

			if (mapping->start > addr ||

			    addr > mapping->last)

				continue;



			*bo = lobj->bo_va->bo;
@@ -1397,8 +1397,8 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
		}



		list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {

			if (mapping->it.start > addr ||

			    addr > mapping->it.last)

			if (mapping->start > addr ||

			    addr > mapping->last)

				continue;



			*bo = lobj->bo_va->bo;