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Commit 01627d96 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes-intel' of git://people.freedesktop.org/~airlied/linux 

Pull drm update from Dave Airlie:
 "This pull just contains a forward of the Intel fixes from Daniel.

  The only annoyance is the RC6 enable, which really should have made
  -next, but since Ubuntu are shipping it I reckon its getting a good
  testing now by the time 3.4 comes out.

  The pull from Daniel contains his pull message to me:

    "A few patches for 3.4, major part is 3 regression fixes:
     - ppgtt broke hibernate on snb/ivb.  Somehow our QA claims that it
       still works, which is why this has not been caught earlier.
     - ppgtt flails in combination with dmar.  I kinda expected this one :(
     - fence handling bugfix for gen2/3.  Iirc this one is about a year
       old, fix curtesy Chris Wilson.  I've created an shockingly simple
       i-g-t test to catch this in the future."

     Wrt regressions I've just got a report that gmbus (newly enabled
     again in 3.4) is a bit noisy.  I'm looking into this atm.

     Also included are the rc6 enable patches for snb from Eugeni.  I
     wanted to include these in the main 3.4 pull but screwed it up.
     Please hit me.  Imo these kind of patches really should go in
     before -rc1, but in thise case rc6 has brought us tons of press and
     guinea pigs^W^W testers and ubuntu is already running with it.  So
     I estimate a pretty small chance for this to blow up.

     And some smaller things:
      - two minor locking snafus
      - server gt2 ivb pciid
      - 2 patches to sanitize the register state left behind by the bios
        some more
      - 2 new quirk entries
      - cs readback trick against missed IRQs from ivb also enabled on snb
      - sprite fix from Jesse"

Let's see if the "enable RC6 on sandybridge" finally works and sticks.
I've been enabling it by hand (i915.i915_enable_rc6=1) for several
months on my Macbook Air, and it definitely makes a difference (and has
worked for me).  But every time we enabled it before it showed some odd
hw buglet for *somebody*.

This time it's all good, I'm sure.

* 'drm-fixes-intel' of git://people.freedesktop.org/~airlied/linux:
  drm/i915: treat src w & h as fixed point in sprite handling code
  drm/i915: no-lvds quirk on MSI DC500
  drm/i915: Add lock on drm_helper_resume_force_mode
  drm/i915: don't leak struct_mutex lock on ppgtt init failures
  drm/i915: disable ppgtt on snb when dmar is enabled
  drm/i915: add Ivy Bridge GT2 Server entries
  drm/i915: properly clear SSC1 bit in the pch refclock init code
  drm/i915: apply CS reg readback trick against missed IRQ on snb
  drm/i915: quirk away broken OpRegion VBT
  drm/i915: enable plain RC6 on Sandy Bridge by default
  drm/i915: allow to select rc6 modes via kernel parameter
  drm/i915: Mark untiled BLT commands as fenced on gen2/3
  drm/i915: properly restore the ppgtt page directory on resume
  drm/i915: Sanitize BIOS debugging bits from PIPECONF
parents e1a7eb08 e37acc0f

drivers/char/agp/intel-agp.h

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ 
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG		0x016A



int intel_gmch_probe(struct pci_dev *pdev,

			       struct agp_bridge_data *bridge);

drivers/char/agp/intel-gtt.c

+2 −1
Original line number Diff line number Diff line
@@ -1190,7 +1190,6 @@ static inline int needs_idle_maps(void) 
{

#ifdef CONFIG_INTEL_IOMMU

	const unsigned short gpu_devid = intel_private.pcidev->device;

	extern int intel_iommu_gfx_mapped;



	/* Query intel_iommu to see if we need the workaround. Presumably that

	 * was loaded first.
@@ -1459,6 +1458,8 @@ static const struct intel_gtt_driver_description { 
	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ 0, NULL, NULL }

};

drivers/gpu/drm/i915/i915_dma.c

+19 −2
Original line number Diff line number Diff line
@@ -1183,6 +1183,21 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) 
	return can_switch;

}



static bool

intel_enable_ppgtt(struct drm_device *dev)

{

	if (i915_enable_ppgtt >= 0)

		return i915_enable_ppgtt;



#ifdef CONFIG_INTEL_IOMMU

	/* Disable ppgtt on SNB if VT-d is on. */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)

		return false;

#endif



	return true;

}



static int i915_load_gem_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1197,7 +1212,7 @@ static int i915_load_gem_init(struct drm_device *dev) 
	drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);



	mutex_lock(&dev->struct_mutex);

	if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) {

	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {

		/* PPGTT pdes are stolen from global gtt ptes, so shrink the

		 * aperture accordingly when using aliasing ppgtt. */

		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
@@ -1207,8 +1222,10 @@ static int i915_load_gem_init(struct drm_device *dev) 
		i915_gem_do_init(dev, 0, mappable_size, gtt_size);



		ret = i915_gem_init_aliasing_ppgtt(dev);

		if (ret)

		if (ret) {

			mutex_unlock(&dev->struct_mutex);

			return ret;

		}

	} else {

		/* Let GEM Manage all of the aperture.

		 *

drivers/gpu/drm/i915/i915_drv.c

+10 −3
Original line number Diff line number Diff line
@@ -66,7 +66,11 @@ MODULE_PARM_DESC(semaphores, 
int i915_enable_rc6 __read_mostly = -1;

module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);

MODULE_PARM_DESC(i915_enable_rc6,

		"Enable power-saving render C-state 6 (default: -1 (use per-chip default)");

		"Enable power-saving render C-state 6. "

		"Different stages can be selected via bitmask values "

		"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "

		"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "

		"default: -1 (use per-chip default)");



int i915_enable_fbc __read_mostly = -1;

module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
@@ -103,8 +107,8 @@ MODULE_PARM_DESC(enable_hangcheck, 
		"WARNING: Disabling this can cause system wide hangs. "

		"(default: true)");



bool i915_enable_ppgtt __read_mostly = 1;

module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);

int i915_enable_ppgtt __read_mostly = -1;

module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);

MODULE_PARM_DESC(i915_enable_ppgtt,

		"Enable PPGTT (default: true)");
@@ -292,6 +296,7 @@ static const struct pci_device_id pciidlist[] = { /* aka */ 
	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */

	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */

	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */

	{0, 0, 0}

};
@@ -533,7 +538,9 @@ static int i915_drm_thaw(struct drm_device *dev) 
		drm_irq_install(dev);



		/* Resume the modeset for every activated CRTC */

		mutex_lock(&dev->mode_config.mutex);

		drm_helper_resume_force_mode(dev);

		mutex_unlock(&dev->mode_config.mutex);



		if (IS_IRONLAKE_M(dev))

			ironlake_enable_rc6(dev);

drivers/gpu/drm/i915/i915_drv.h

+22 −1
Original line number Diff line number Diff line
@@ -1053,6 +1053,27 @@ struct drm_i915_file_private { 


#include "i915_trace.h"



/**

 * RC6 is a special power stage which allows the GPU to enter an very

 * low-voltage mode when idle, using down to 0V while at this stage.  This

 * stage is entered automatically when the GPU is idle when RC6 support is

 * enabled, and as soon as new workload arises GPU wakes up automatically as well.

 *

 * There are different RC6 modes available in Intel GPU, which differentiate

 * among each other with the latency required to enter and leave RC6 and

 * voltage consumed by the GPU in different states.

 *

 * The combination of the following flags define which states GPU is allowed

 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and

 * RC6pp is deepest RC6. Their support by hardware varies according to the

 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one

 * which brings the most power savings; deeper states save more power, but

 * require higher latency to switch to and wake up.

 */

#define INTEL_RC6_ENABLE			(1<<0)

#define INTEL_RC6p_ENABLE			(1<<1)

#define INTEL_RC6pp_ENABLE			(1<<2)



extern struct drm_ioctl_desc i915_ioctls[];

extern int i915_max_ioctl;

extern unsigned int i915_fbpercrtc __always_unused;
@@ -1065,7 +1086,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly; 
extern int i915_enable_rc6 __read_mostly;

extern int i915_enable_fbc __read_mostly;

extern bool i915_enable_hangcheck __read_mostly;

extern bool i915_enable_ppgtt __read_mostly;

extern int i915_enable_ppgtt __read_mostly;



extern int i915_suspend(struct drm_device *dev, pm_message_t state);

extern int i915_resume(struct drm_device *dev);