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Commit 013bf292 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk qcom: clk-alpha-pll: Update to use determine rate ops for PLL"

parents 7d00b40a 6ff60745

drivers/clk/qcom/clk-alpha-pll.c

+12 −4
Original line number Diff line number Diff line
@@ -904,12 +904,20 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,

					unsigned long *prate)

static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,

				struct clk_rate_request *req)

{

	unsigned long rrate, prate;

	u32 l, a;



	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);

	prate = clk_hw_get_rate(clk_hw_get_parent(hw));

	rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);



	req->best_parent_hw = clk_hw_get_parent(hw);

	req->best_parent_rate = prate;

	req->rate = rrate;



	return 0;

}



static void clk_huayra_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
@@ -1303,7 +1311,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { 
	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_huayra_recalc_rate,

	.round_rate = alpha_pll_huayra_round_rate,

	.determine_rate = alpha_pll_huayra_determine_rate,

	.set_rate = alpha_pll_huayra_set_rate,

	.list_registers = clk_huayra_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

drivers/clk/qcom/clk-rcg2.c

+5 −5
Original line number Diff line number Diff line
@@ -239,19 +239,19 @@ static void disable_unprepare_rcg_srcs(struct clk *curr, struct clk *new) 
static unsigned long

calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)

{

	u64 tmp = rate;



	if (hid_div) {

		rate *= 2;

		rate /= hid_div + 1;

		tmp *= 2;

		do_div(tmp, hid_div + 1);

	}



	if (mode) {

		u64 tmp = rate;

		tmp *= m;

		do_div(tmp, n);

		rate = tmp;

	}



	return rate;

	return tmp;

}



static unsigned long