Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 00bf377d authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pin control fixes from Linus Walleij:
 "Here are a bunch of fixes for pin control.  Just drivers and a
  MAINTAINERS fixup:

   - Driver fixes for i.MX, single register, Tegra and BayTrail.

   - MAINTAINERS entry for the documentation"

* tag 'pinctrl-v4.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: baytrail: Fix mingled clock pins
  MAINTAINERS: belong Documentation/pinctrl.txt properly
  pinctrl: tegra: Fix build dependency
  gpio: tegra: Make lockdep class file-scoped
  pinctrl: single: Fix missing flush of posted write for a wakeirq
  pinctrl: imx: Do not treat a PIN without MUX register as an error
parents 52827f38 b41aa4f8
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -8963,6 +8963,7 @@ L: linux-gpio@vger.kernel.org
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
S:	Maintained
F:	Documentation/devicetree/bindings/pinctrl/
F:	Documentation/pinctrl.txt
F:	drivers/pinctrl/
F:	include/linux/pinctrl/

+7 −2
Original line number Diff line number Diff line
@@ -98,7 +98,6 @@ struct tegra_gpio_info {
	const struct tegra_gpio_soc_config	*soc;
	struct gpio_chip			gc;
	struct irq_chip				ic;
	struct lock_class_key			lock_class;
	u32					bank_count;
};

@@ -547,6 +546,12 @@ static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

/*
 * This lock class tells lockdep that GPIO irqs are in a different category
 * than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int tegra_gpio_probe(struct platform_device *pdev)
{
	const struct tegra_gpio_soc_config *config;
@@ -660,7 +665,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)

		bank = &tgi->bank_info[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &tgi->lock_class);
		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
	}
+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF)	+= sirf/
obj-$(CONFIG_PINCTRL_TEGRA)	+= tegra/
obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
obj-$(CONFIG_PINCTRL_TZ1090)	+= pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_TZ1090_PDC)	+= pinctrl-tz1090-pdc.o
obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
+2 −2
Original line number Diff line number Diff line
@@ -209,9 +209,9 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
		pin_reg = &info->pin_regs[pin_id];

		if (pin_reg->mux_reg == -1) {
			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
			dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
				info->pins[pin_id].name);
			return -EINVAL;
			continue;
		}

		if (info->flags & SHARE_MUX_CONF_REG) {
+3 −3
Original line number Diff line number Diff line
@@ -401,9 +401,9 @@ static const struct byt_simple_func_mux byt_score_sata_mux[] = {
static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
static const unsigned int byt_score_plt_clk4_pins[] = { 99 };
static const unsigned int byt_score_plt_clk5_pins[] = { 100 };
static const unsigned int byt_score_plt_clk3_pins[] = { 101 };
static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
	SIMPLE_FUNC("plt_clk", 1),
};
Loading